SLG46200 datasheet(47/69 Pages) DIALOG

Teilenummer	SLG46200

Bauteilbeschribung	GreenPAK Programmable Mixed Signal Array

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000-0046200-124

Page 42 of 64

SLG46200

17.1 Delay Cells Functional Diagram

17.2 Delay Timing

The delay timing of each logic cell is determined by the frequency of the RC Oscillator and the Delay Time Control registers which

use Counter data values: reg<432:419> (CNT0 data) for DLY0 , reg<446:433> (CNT1 data) for DLY1, reg<460:447> (CNT2 data)

for DLY2. The formulas below list the timing delay equations for each logic cell;

For DLY0:

TDLY0 = (1/FOSC) * (reg<432:419> + 1)

For DLY1:

TDLY1 = (1/FOSC) * (reg<446:433> + 1)

For DLY2:

TDLY2 = (1/FOSC) * (reg<460:447> + 1)

Note: In order for these equations above to be valid the pulse width must be larger than the total rising and falling

edge delay times. Also, for proper functionality of each Delay cell, each respective CNTx_d<13:0> must have

a value of greater than ‘1’.

Figure 29. Delay Cells Functional Diagram

Delay0

reg <469:468>

reg <412>

reg <474>

reg <432:419>

From Connection Matrix

Dly_in0

DLY0_dt<13:0>

DLY0_opath_s

DLY0_mode_s

DLY0_d_mode_s

Dly_out0

To Connection Matrix

Delay1

reg <471:470>

reg <475>

reg <446:433>

From Connection Matrix

Dly_in1

DLY1_dt<13:0>

DLY1_opath_s

DLY1_d_mode_s

Dly_out1

To Connection Matrix

Delay2

reg <473:472>

reg <476>

reg <440:447

From Connection Matrix

Dly_in2

DLY2_dt<13:0>

DLY2_opath_s

DLY2_d_mode_s

Dly_out2

To Connection Matrix

reg <478>

DLY_in_s

reg <478>

DLY_in_s

OUT

DLY IN

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