SLG46200 datasheet(31/69 Pages) DIALOG

Teilenummer	SLG46200

Bauteilbeschribung	GreenPAK Programmable Mixed Signal Array

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31 / 69 page

000-0046200-124

Page 26 of 64

SLG46200

11.10 ADC Register Settings

Figure 14. ADC Output Timing (power on signal comes from register)

Table 11. ADC Register Settings

Signal Name

Signal Function

Register Bit

Address

Register Definition

ADC_mux_en

ADC analog input mux

enable

<339>

0: No change

1: Mux enable

ADC_clk_sel

ADC clock selection

<340>

0: Internal oscillator

1: External clock from PIN 4

ADC_Vref_sel

VREF setting

<342:341>

00: Bandgap (1.796V from internal source)

01: External voltage source

10: Power divider (VDD* 0.547)

ADC_sel

ADC mode select

<350>

0: Single-ended operation using PIN 6

1: Differential mode operation using PIN 6 & PIN 7

Note: For Pseudo-Differential mode, reg <351:350> will be

set to “11”

ADC_gain_control

ADC PGA gain control

<353:351>

000: Single-ended (0.5X gain) or differential (N/A)

001: Single-ended (1X gain) or differential (1x gain)

010: Single-ended (2X gain) or differential (2X gain)

011: Single-ended (4X gain) or differential (4X gain)

100: Single-ended (8X gain) or differential (8X gain)

101: Single-ended (N/A) or differential (16X gain)

ADC_DAC_Vref

ADC reference DAC

feedback select

<362>

0: Normal

1: 0.5x gain (use this setting when VREF is externally

selected)

ADC_gndoff_en

ADC pseudo diff input

enable under ADC diff

mode

<371>

0: N/A

1: Enable

Pin3_dig_out

PIN 3 digital output

source selection

<373:372>

00/01: From connection matrix output <12>

10: Serial data from the S2P

11: Serial data from the ADC

123456789

10

11

12

13

14

15

16

CLK

B7

B0

SER DATA

PAR DATA

16 cycles

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