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CY7C1461KV33 Datenblatt(PDF) 14 Page - Cypress Semiconductor

Teilenummer CY7C1461KV33
Bauteilbeschribung  36-Mbit (1M36/2M18) Flow-Through SRAM with NoBL??Architecture
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Hersteller  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1461KV33 Datenblatt(HTML) 14 Page - Cypress Semiconductor

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CY7C1461KV33
CY7C1463KV33
Document Number: 001-66681 Rev. *G
Page 14 of 23
Capacitance
In the following table, the capacitance parameters are listed.
Parameter [12]
Description
Test Conditions
100-pin TQFP
Max
Unit
CIN
Input capacitance
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
5
pF
CCLK
Clock input capacitance
5
pF
CIO
Input/output capacitance
5
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
Parameter [12]
Description
Test Conditions
100-pin TQFP
Package
Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test
methods
and
procedures
for
measuring thermal impedance,
per EIA/JESD51.
With Still Air (0 m/s)
35.36
°C/W
With Air Flow (1 m/s)
31.30
°C/W
With Air Flow (3 m/s)
28.86
°C/W
JC
Thermal resistance
(junction to case)
–7.52
°C/W
JB
Thermal resistance
(junction to board)
28.89
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
OUTPUT
R = 317
R = 351
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
RL = 50
Z0 = 50 
VT= 1.5 V
3.3 V
ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
2 V/ns
 1 ns
(c)
OUTPUT
R = 1667
R = 1538
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
RL = 50 
Z0 = 50 
VT = 1.25 V
2.5 V
ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
2 V/ns
 1 ns
(c)
3.3 V I/O Test Load
2.5 V I/O Test Load
Note
12. Tested initially and after any design or process change that may affect these parameters.


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