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CY7C1563XV18 Datenblatt(PDF) 23 Page - Cypress Semiconductor

Teilenummer CY7C1563XV18
Bauteilbeschribung  72-Mbit QDR짰 II Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
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Hersteller  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1563XV18 Datenblatt(HTML) 23 Page - Cypress Semiconductor

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Document Number: 001-70205 Rev. *G
Page 23 of 29
CY7C1563XV18/CY7C1565XV18
Switching Characteristics
Over the Operating Range
Parameter [29, 30]
Description
633 MHz
600 MHz
Unit
Cypress
Parameter
Consortium
Parameter
Min
Max
Min
Max
tPOWER
VDD(typical) to the first access [31]
1
1
ms
tCYC
tKHKH
K clock cycle time
1.58
8.4
1.66
8.4
ns
tKH
tKHKL
Input clock (K/K) HIGH
0.4
0.4
ns
tKL
tKLKH
Input clock (K/K) LOW
0.4
0.4
ns
tKHKH
tKHKH
K clock rise to K clock rise (rising edge to rising edge)
0.71
0.75
ns
Setup Times
tSA
tAVKH
Address setup to K clock rise
0.23
0.23
ns
tSC
tIVKH
Control setup to K clock rise (RPS, WPS)
0.23
0.23
ns
tSCDDR
tIVKH
Double data rate control setup to clock (K/K) rise (BWS0, BWS1,
BWS2, BWS3)
0.18
0.18
ns
tSD
tDVKH
D[X:0] setup to clock (K/K) rise
0.18
0.18
ns
Hold Times
tHA
tKHAX
Address hold after K clock rise
0.23
0.23
ns
tHC
tKHIX
Control hold after K clock rise (RPS, WPS)
0.23
0.23
ns
tHCDDR
tKHIX
Double data rate control hold after clock (K/K) rise (BWS0, BWS1,
BWS2, BWS3)
0.18
0.18
ns
tHD
tKHDX
D[X:0] Hold after clock (K/K) rise
0.18
0.18
ns
Output Times
tCCQO
tCHCQV
K/K clock rise to echo clock valid
0.45
0.45
ns
tCQOH
tCHCQX
Echo clock hold after K/K clock rise
–0.45
–0.45
ns
tCQD
tCQHQV
Echo clock high to data valid
0.09
0.09
ns
tCQDOH
tCQHQX
Echo clock high to data invalid
–0.09
–0.09
ns
tCQH
tCQHCQL
Output clock (CQ/CQ) HIGH [32]
0.71
0.75
ns
tCQHCQH
tCQHCQH
CQ clock rise to CQ clock rise (rising edge to rising edge) [32]
0.71
0.75
ns
tCHZ
tCHQZ
Clock (K/K) rise to high Z (active to high Z) [33, 34]
0.45
0.45
ns
tCLZ
tCHQX1
Clock (K/K) rise to low Z [33, 34]
–0.45
–0.45
ns
tQVLD
tCQHQVLD
Echo clock high to QVLD valid [35]
–0.15 0.15 –0.15 0.15
ns
PLL Timing
tKC Var
tKC Var
Clock phase jitter
0.15
0.15
ns
tKC lock
tKC lock
PLL lock time (K)
100
100
s
tKC Reset
tKC Reset
K static to PLL reset [36]
30
30
ns
Notes
29. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250
, VDDQ = 1.5 V, input
pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5 on page 22.
30. When a part with a maximum frequency above 600 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
31. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD(minimum) initially before a read or write operation can be
initiated.
32. These parameters are extrapolated from the input timing parameters (tCYC/2 – 80 ps, where 80 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
33. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 22. Transition is measured ± 100 mV from steady-state voltage.
34. At any voltage and temperature tCHZ is less than tCLZ.
35. tQVLD spec is applicable for both rising and falling edges of QVLD signal.
36. Hold to >VIH or <VIL.


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