CY7C1648KV18 datasheet(16/29 Pages) CYPRESS

Teilenummer	CY7C1648KV18

Bauteilbeschribung	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

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Hersteller	CYPRESS [Cypress Semiconductor]

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Document Number: 001-44061 Rev. *L

Page 16 of 29

CY7C1648KV18

CY7C1650KV18

Identification Register Definitions

Instruction Field

Value

Description

CY7C1648KV18

CY7C1650KV18

Revision number (31:29)

000

Version number.

Cypress device ID (28:12)

11010111100010011

11010111100100011

Defines the type of SRAM.

Cypress JEDEC ID (11:1)

00000110100

Enables unique identification of SRAM

vendor.

ID register presence (0)

1

Indicates the presence of an ID register.

Scan Register Sizes

Register Name

Bit Size

Instruction

3

Bypass

1

ID

32

Boundary Scan

109

Instruction Codes

Instruction

Code

Description

EXTEST

000

Captures the input and output ring contents.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the input and output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

100

Captures the input and output ring contents. Places the boundary scan register between TDI

and TDO. Does not affect the SRAM operation.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

RESERVED

110

Do Not Use: This instruction is reserved for future use.

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

Ähnliche Beschreibung - CY7C1648KV18

Hersteller	Teilenummer	Datenblatt	Bauteilbeschribung
Cypress Semiconductor	CY7C1648KV18	857Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C1668KV18	771Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1548KV18	844Kb / 29P	72-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C2670KV18	824Kb / 30P	144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Renesas Technology Corp	R1QHA4436RBG	916Kb / 30P	144-Mbit DDR?줚I SRAM 2-word Burst Architecture (2.0 Cycle Read latency)
Cypress Semiconductor	CY7C2644KV18	840Kb / 30P	144-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
	CY7C1643KV18	861Kb / 31P	144-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C2642KV18	885Kb / 30P	144-Mbit QDR짰 II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
	CY7C1166KV18	874Kb / 29P	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1546KV18	959Kb / 31P	72-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

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