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MC100EP210S Datenblatt(PDF) 1 Page - ON Semiconductor |
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MC100EP210S Datenblatt(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2002 May, 2002 – Rev. 5 1 Publication Order Number: MC100EP210S/D MC100EP210S 2.5V1:5 Dual Differential LVDS Compatible Clock Driver The MC100EP210S is a low skew 1–to–5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to five identical differential LVDS outputs. The EP210S specifically guarantees low output–to–output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. Two internal 50 W resistors are provided across the inputs. For LVDS inputs, VTA and VTB pins should be unconnected. For LVPECL inputs, VTA and VTB pins should be connected to the VTT (VCC–2.0 V) supply. Designers can take advantage of the EP210S performance to distribute low skew LVDS clocks across the backplane or the board. Special considerations are required for differential inputs under No Signal conditions to prevent instability. • 20 ps Typical Output–to–Output Skew • 85 ps Typical Device–to–Device Skew • 550 ps Typical Propagation Delay • The 100 Series Contains Temperature Compensation • Maximum Frequency > 1 GHz Typical • Operating Range: V CC = 2.375 V to 2.625 V with VEE = 0 V • Internal 50 W Input Termination Resistors • LVDS Input/Output Compatible 32 1 MC100 AWLYYWW EP210S Device Package Shipping ORDERING INFORMATION LQFP–32 FA SUFFIX CASE 873A MARKING DIAGRAM* A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week *For additional information, refer to Application Note AND8002/D MC100EP210SFA LQFP–32 250 Units/Tray MC100EP210SFAR2 LQFP–32 2000 Tape & Reel http://onsemi.com |
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