Datenblatt-Suchmaschine für elektronische Bauteile |
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BTS7020-2EPA Datenblatt(PDF) 33 Page - Infineon Technologies AG |
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BTS7020-2EPA Datenblatt(HTML) 33 Page - Infineon Technologies AG |
33 / 58 page Data Sheet 33 Rev. 1.00 2017-08-24 BTS7020-2EPA PROFETTM+2 Protection The channel is allowed to switch ON for nRETRY(CR) times before switching OFF. After a time tRETRY, if the input pin is set to “high”, the channel switches ON again for nRETRY(NT) times before switching OFF again (“retry” cycle). After nRETRY(CYC) consecutive “retry” cycles, the channel latches OFF. It is necessary to set the input pin to “low” for a time longer than tDELAY(CR) to de-latch the channel (“counter reset delay” time) and to reset the internal counter to the default value. During the “counter reset delay” time, if the input is set to “high” the channel remains switched OFF and the timer counting tDELAY(CR) is reset, starting to count again as soon as the input pin is set to “low” again. If the input pin remains “low” for a time longer than tDELAY(CR) the internal retry counter is reset to the default value, allowing nRETRY(CR) retries at the next channel activation. The retry strategy is shown in Figure 29 (flowchart), Figure 27 (timing diagram - input pin always “high”) and Figure 28 (timing diagram - channel controlled in PWM). Figure 27 Retry Strategy Timing Diagram Figure 28 Retry Strategy Timing Diagram - Channel operated in PWM t IN tRETRY Short circu it to ground IL 0 1 nRETRY(CR) Internal counter nRETRY(CR) + nRETRY(NT) nRETRY(CR) + (nRETRY(CYC) * nRETRY(NT)) tDELAY(CR) tRETRY 0 nRETRY(CR) nRETRY(NT) "retry" cycle nRETRY(NT) t t t Protection_PROFET_time_noPWM.emf nRETRY(CYC) t DEN t IIS IIS(FAULT) IL / kILIS IL / kILIS t IN tRETRY Short circu it to ground IL 0 1 nRETRY(CR) In ternal counter nRETRY(CR) + nRETRY(NT) nRETRY(CR) + (nRETRY(CYC) * nRETRY(NT)) tDELAY(CR) tRETRY 0 nRETRY(CR) nRETRY(NT) "retry" cycle nRETRY(NT) t t t Protection_PROFET_Timings.emf nRETRY(CYC) |
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