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KFW4G16U2M-DEB6 Datenblatt(PDF) 3 Page - Samsung semiconductor

Teilenummer KFW4G16U2M-DEB6
Bauteilbeschribung  FLASH MEMORY(54MHz)
Download  125 Pages
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Hersteller  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KFW4G16U2M-DEB6 Datenblatt(HTML) 3 Page - Samsung semiconductor

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OneNAND1G(KFG1G16Q2M-DEB5)
FLASH MEMORY
3
OneNAND2G(KFH2G16Q2M-DEB5)
OneNAND4G(KFW4G16Q2M-DEB5)
Document Title
OneNAND
Revision History
Revision No.
0.0
0.1
0.2
0.3
0.4
0.4.1
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
Draft Date
Oct. 26, 2004
Dec. 7, 2004
Dec. 24, 2004
Jan. 10, 2005
Feb. 25, 2005
Mar. 2, 2005
History
Initial Issue.
1. Corrected Errata
2. Revised cache read flow chart
3. Revised standby current
4. Revised spare area description
5. Added CE don’t care state for Asynch Write, Load, Program, and Block
Erase timing diagram
1. Corrected Errata
2. Added Copy-back Program Operation With Random Data Input
3. Pended Active Erase Current
4. Changed tBA from 11ns to 11.5ns
1. Corrected the errata
2. Revised typical value of ISB from 50uA to 10uA
3. Revised maximum value of ISB from 100uA to 50uA
4. Revised erase current as TBD
5. Revised maximum value of tCE, tAA and tACC from 70ns to 76ns
6. Revised Vcc-IO description
7. Revised Spare Area description
8. Added extra information on Controller Status Register
9. Added commands related to Interrupt Status Register bits
10. Revised Write Protection Status on Chapter 3.4.3
11. Revised Copy-Back Program Operation description
12. Added extra information on Multi-Block Erase Operation
13. Disabled FBA restriction in OTP operation
14. Revised Cache Read Flow Chart
15. Added ISB information on DDP
16. Revised Reset Parameter descriptions
17. Added RDY information on Warm Reset Timing diagram
18. Added information on Data Protection Timing During Power Down
19. Revised Interrupt pin rise and falling slope graph
20. Added restriction on address register setting on Dual Operations
21. Added restriction on address register setting on Cache Read Operation
1. Corrected the errata
2. Updated DC parameters to RMS values
3. Added QDP feature
4. Added Speed Information on Product Number
5. Revised tOEZ description
6. Revised OTP register setting restriction
7. Added ILI, ILO and ISB information on QDP
8. Added Boot Sequence Infrormation on Technical Notes
9. Added Cint Information
1. Revised OTP Load Operation Flow Chart
1.1
Revision History


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