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TL16C2550PFB Datenblatt(PDF) 1 Page - Texas Instruments |
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TL16C2550PFB Datenblatt(HTML) 1 Page - Texas Instruments |
1 / 34 page www.ti.com FEATURES APPLICATIONS DESCRIPTION TL16C2550 SLWS161 – JUNE 2005 2.5-V to 5-V DUAL UART WITH 16-BYTE FIFOS • Internal Diagnostic Capabilities: • Programmable Auto-RTS and Auto-CTS – Loopback Controls for Communications Link Fault Isolation • In Auto-CTS Mode, CTS Controls Transmitter – Break, Parity, Overrun, and Framing Error • In Auto-RTS Mode, RCV FIFO Contents and Simulation Threshold Control RTS • Fully Prioritized Interrupt System Controls • Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on • Modem Control Functions (CTS, RTS, DSR, the Same Power Drop DTR, RI, and DCD) • Capable of Running With All Existing • Available in 48-Pin TQFP (PFB), 44-Pin PLCC TL16C450 Software (FN), or 32-Pin QFN (RHB) Packages • After Reset, All Registers Are Identical to the • Pin Compatible with TL16C752B (48-Pin TL16C450 Register Set Package) • Up to 24-MHz Clock Rate for up to 1.5-Mbaud Operation With VCC = 5 V • Point-of-Sale Terminals • Up to 20-MHz Clock Rate for up to 1.25-Mbaud • Gaming Terminals Operation With VCC = 3.3 V • Portable Applications • Up to 16-MHz Clock Rate for up to 1-Mbaud • Router Control Operation With VCC = 2.5 V • Cellular Data • In the TL16C450 Mode, Hold and Shift • Factory Automation Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data • Programmable Baud Rate Generator Allows The TL16C2550 is a dual universal asynchronous Division of Any Input Reference Clock by 1 to receiver and transmitter (UART). It incorporates the functionality of two TL16C550D UARTs, each UART (216 - 1) and Generates an Internal 16 × Clock having its own register set and FIFOs. The two • Standard Asynchronous Communication Bits UARTs share only the data bus interface and clock (Start, Stop, and Parity) Added to or Deleted source, otherwise they operate independently. From the Serial Data Stream Another name for the uart function is Asynchronous • 5-V, 3.3-V, and 2.5-V Operation Communications Element (ACE), and these terms will be used interchangeably. The bulk of this document • Independent Receiver Clock Input will describe the behavior of each ACE, with the • Transmit, Receive, Line Status, and Data Set understanding that two such devices are incorporated Interrupts Independently Controlled into the TL16C2550. • Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (dc to 1 Mbit/s) • False-Start Bit Detection • Complete Status Reporting Capabilities • 3-State Output TTL Drive Capabilities for Bidirectional Data Bus and Control Bus • Line Break Generation and Detection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the forma- Copyright © 2005, Texas Instruments Incorporated tive or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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