Datenblatt-Suchmaschine für elektronische Bauteile |
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MAX8725ETI Datenblatt(PDF) 28 Page - Maxim Integrated Products |
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MAX8725ETI Datenblatt(HTML) 28 Page - Maxim Integrated Products |
28 / 30 page Multichemistry Battery Chargers with Automatic System Power Selector 28 ______________________________________________________________________________________ The ripple current is determined by: ∆IL = VBATT tOFF / L where: tOFF = 2.5µs (VDCIN - VBATT) / VDCIN for VBATT < 0.88 VDCIN or: tOFF = 0.3µs for VBATT > 0.88 VDCIN Figure 11 illustrates the variation of the ripple current vs. battery voltage when the circuit is charging at 3A with a fixed input voltage of 19V. Higher inductor values decrease the ripple current. Smaller inductor values require high-saturation current capabilities and degrade efficiency. Designs that set LIR = ∆IL / ICHG = 0.3 usually result in a good balance between inductor size and efficiency. Input-Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. Nontantalum chemistries (ceramic, aluminum, or OS- CON) are preferred due to their resilience to power-up surge currents. The input capacitors should be sized so that the temperature rise due to ripple current in continuous conduction does not exceed approximately 10°C. The maximum ripple current occurs at 50% duty factor or VDCIN = 2 ✕ VBATT, which equates to 0.5 ✕ ICHG. If the application of interest does not achieve the maximum value, size the input capacitors according to the worst-case conditions. Output-Capacitor Selection The output capacitor absorbs the inductor ripple cur- rent and must tolerate the surge current delivered from the battery when it is initially plugged into the charger. As such, both capacitance and ESR are important parameters in specifying the output capacitor as a filter and to ensure the stability of the DC-DC converter (see the Compensation section). Beyond the stability requirements, it is often sufficient to make sure that the output capacitor’s ESR is much lower than the battery’s ESR. Either tantalum or ceramic capacitors can be used on the output. Ceramic devices are preferable because of their good voltage ratings and resilience to surge currents. Applications Information Startup Conditioning Charge for Overdischarged Cells It is desirable to charge deeply discharged Li+ batter- ies at a low rate to improve cycle life. The MAX1909/MAX8725 automatically reduces the charge current when the voltage per cell is below 3.1V. The charge current-sense voltage is set to 4.5mV (ICHG = 300mA with RS2 = 15mΩ) until the battery voltage rises above the threshold. There is approximately 300mV for 3 cell, 400mV for 4 cell of hysteresis to prevent the charge-current magnitude from chattering between the two values. For the MAX8725, control the ICTL voltage to set a con- ditioning charge rate. Layout and Bypassing Bypass DCIN with a 1µF capacitor to ground (Figure 1). D4 protects the MAX1909/MAX8725 when the DC power source input is reversed. A signal diode for D4 is adequate because DCIN only powers the LDO and the internal reference. Bypass LDO, DHIV, DLOV, and other pins as shown in Figure 1. Good PC board layout is required to achieve specified noise, efficiency, and stable performance. The PC board layout artist must be given explicit instructions— preferably, a sketch showing the placement of the power-switching components and high-current routing. Refer to the PC board layout in the MAX1909/MAX8725 evaluation kit for examples. A ground plane is essential for optimum performance. In most applications, the cir- cuit is located on a multilayer board, and full use of the four or more copper layers is recommended. Use the top layer for high-current connections, the bottom layer for quiet connections, and the inner layers for an unin- terrupted ground plane. Use the following step-by-step guide: 1) Place the high-power connections first, with their grounds adjacent: a) Minimize the current-sense resistor trace lengths, and ensure accurate current sensing with Kelvin connections. b) Minimize ground trace lengths in the high-current paths. c) Minimize other trace lengths in the high-current paths. d) Use > 5mm wide traces. II VV V V RMS CHG BATT DCIN BATT DCIN = − () |
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