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H27UCG8T2BTR-BC Datenblatt(Datasheet) 20 Page - Hynix Semiconductor

Teile-Nr. H27UCG8T2BTR-BC
Beschreibung  64Gb(8192M x 8bit) MLC NAND Flash
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Hersteller  HYNIX [Hynix Semiconductor]
Homepage  http://www.skhynix.com/ko/index.jsp
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H27UCG8T2BTR-BC
64Gb(8192M x 8bit) MLC NAND Flash
Rev 0.1 / Oct. 2012
20
Notes:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us.
2. Program / Erase Enable Operation: WP# high to WE# High.
Program / Erase Disable Operation: WP# Low to WE# High.
3. The transition of the corresponding control pins must occur only while WE# is held low.
4. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first
data cycle.
I/O
Page
Program
Block
Erase
Read
Cache
Read
Cache
Program
Coding
70h / 78h
0
Pass / Fail
Pass / Fail
N/A
N/A
Pass /
Fail (N)
N page
Pass : „0‟ Fail : „1‟
1
N/A
N/A
N/A
N/A
Pass /
Fail (N-1)
N -1 page
Pass : „0‟ Fail : „1‟
2
N/A
N/A
N/A
N/A
N/A
„0‟
3
N/A
N/A
N/A
N/A
N/A
„0‟
4
N/A
N/A
N/A
N/A
N/A
„0‟
5
N/A
N/A
N/A
Ready /
Busy
Ready /
Busy
Ready / Busy
Busy : „0‟ Ready : „1‟
6
Ready /
Busy
Ready /
Busy
Ready /
Busy
Ready /
Busy
Ready /
Busy
Data Cache Ready / Busy
Busy : „0‟ Ready : „1‟
7
Write
Protect
Write
Protect
Write
Protect
Write
Protect
Write
Protect
Protected : „0‟
Not Protected : „1‟
Notes:
1. I/O0 : This bit is only valid for Program and Erase operations. During Cache Program operations,
this bit is only valid when I/O5 is set to one.
2. I/O1 : This bit is only valid for cache program operations. This bit is not valid until after the second
15h command or the 10h command has been transferred in a Cache program sequence.
When Cache program is not supported, this bit is not used.
3. I/O5 : If set to one, then there is no array operation in progress. If cleared to zero, then there is a
command being processed (I/O6 is cleared to zero) or an array operation in progress. When
overlapped interleaved operations or cache commands are not supported, this bit is not used.
4. I/O6 : If set to one, then the device or interleaved address is ready for another command and all
other bits in the status value are valid. If cleared to zero, then the last command issued is not
yet complete and Status Register bits<5:0> are invalid value. When cache operations are in
use, then this bit indicates whether another command can be accepted, and I/O5 indicates
whether the last operation is complete.
2.8. Status Register Coding
2.8.1. Status Register Coding For 70h/78h command




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