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H27UCG8T2BTR-BC Datenblatt(Datasheet) 4 Page - Hynix Semiconductor

Teile-Nr. H27UCG8T2BTR-BC
Beschreibung  64Gb(8192M x 8bit) MLC NAND Flash
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Hersteller  HYNIX [Hynix Semiconductor]
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H27UCG8T2BTR-BC
64Gb(8192M x 8bit) MLC NAND Flash
Rev 0.1 / Oct. 2012
4
1. Summary Description ……………………………………………………………………………………………..
1.1. Product List ……..…………………………………………………………………..………………………….….
1.2. Pin Descriptions ..…………………………………………………………………..…………………..…….....
1.3. Pin Diagram ...............................................................................................................................
1.4. Pin Assignments ………………………………………………………………………..……..…………..……..
1.5. Block Diagram ............................................................................................................................
1.6. Array Organization .....................................................................................................................
1.7. Addressing .................................................................................................................................
1.8. Extended Blocks Arrangement ..................................................................................................
1.9. Command Set ……………………………………………………………………………….………………..……
1.10. Mode Selection …………………………………………………………………………….…………………..….
1.11. Bad Block Management ………………………………………………………………….…………………….
1.12. Bad Block Replacement …………………………………………………………………….………………….
2. Electrical Characteristics ……………………………………………………………………...…………………
2.1. Valid Blocks …………………………………………………………………………………………….…………..
2.2. Absolute Maximum Rating ………………………………………………………………………….………….
2.3. DC and Operating Characteristics ……………………………………………………………….……………
2.4. AC Test Conditions …………………………………………………………………………………….………….
2.5. Pin Capacitance (TA=25℃, F=1.0㎒) ..........................................................................................
2.6. Program/ Read / Erase Characteristics .....................................................................................
2.7. AC Timing Characteristics ………………………………………………………………………….…………..
2.8. Status Register Coding ……………………………………………………………………………………….…
2.8.1. Status Register Coding For 70h/78h command ………….…………………………………….…..
2.8.2. Status Register Coding For 75h command ……………………….……………………………….…
2.9. Device Identifier Coding …………………………………………………………………………………….….
2.10. Read ID Data Table ………………………………………………………………………………………….…
2.10.1. 3rd Byte of Device Identifier Description ……………………………………………………………
2.10.2. 4th Byte of Device Identifier Description ……………………………………………………………
2.10.3. 5th Byte of Device Identifier Description ……………………………………………………………
2.10.4. 6th Byte of Device Identifier Description ……………………………………………………………
3. Timing Diagram ………………………………………………………………………………………….………..…
3.1. Command Latch Cycle Timings ……………………………………………………………………….………..
3.2. Address Latch Cycle Timings .………………………………………………………………………….……….
3.3. Input Data Latch Cycle Timings …………………………………………………………………….…………
3.4. Data Output Cycle Timings …………………………………………………………………………….……….
3.5. Data Output Cycle Timings (EDO type) ……………………………………………………………….………
3.6. Read Status Cycle Timings …………………………………………………………………………….……….
3.7. Multi Plane Read Status Timings …………………………………………………………………….……….
3.8. Page Read Operation Timings .……………………………………………………………………….……….
3.9. Page Read Operation Timings (Intercepted by CE#) ………………………………………………….……
3.10. Page Read Operation Timings with CE# don’t care …………………………………………….………
3.11. Random Data Output Timings ………………………………………………………………………….…….
3.12. Multi Plane Page Read Operation with Random Data output Timings ……………………….……
3.13. Cache Read Operation Timings ……………………………………………………………………….……..
3.14. Multi Plane Cache Read Operation Timings ……………………………………………………….……..
3.15. Read ID Operation Timings ……………………………………………………………………………….….
3.16. Page Program Operation Timings ……………………………………………………………………….….
3.17. Page Program Operation Timings with CE# don’t care ………………………………………………..
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