Datenblatt-Suchmaschine für elektronische Bauteile |
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K9F1G08U0E Datenblatt(PDF) 33 Page - Samsung semiconductor |
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K9F1G08U0E Datenblatt(HTML) 33 Page - Samsung semiconductor |
33 / 38 page - 33 - datasheet K9F1G08U0E FLASH MEMORY Rev. 1.11 SAMSUNG CONFIDENTIAL [Figure 7] Random Data Output In a Page 5.2 Page Program The device is programmed basically on a page basis, and each page shall be programmed only once before being erased. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address inputs and then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically exe- cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while program- ming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. [Figure 8] Program & Read Status Operation Address 00h Data Output R/B RE t 30h Address 05h E0h 4Cycles 2Cycles Data Output Data Field Spare Field Data Field Spare Field I/Ox Col. Add.1,2 & Row Add.1,2 Col. Add.1,2 80h R/B Address & Data Input I/O0 Pass Data 10h 70h Fail tPROG I/Ox Col. Add.1,2 & Row Add.1,2 "0" "1" |
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Ähnliche Beschreibung - K9F1G08U0E |
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