Datenblatt-Suchmaschine für elektronische Bauteile |
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GD25B64C Datenblatt(PDF) 16 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B64C Datenblatt(HTML) 16 Page - GigaDevice Semiconductor (Beijing) Inc. |
16 / 57 page 3.3V Uniform Sector Dual and Quad Serial Flash GD25B64C 16 7.1. Write Enable (WREN) (06H) The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR) and Erase/Program Security Registers command. The Write Enable (WREN) command sequence: CS# goes low sending the Write Enable command CS# goes high. Figure 1. Write Enable Sequence Diagram 7.2. Write Disable (WRDI) (04H) The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence: CS# goes low Sending the Write Disable command CS# goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase, Erase/Program Security Registers and Reset commands. Figure 2. Write Disable Sequence Diagram Command 0 1 2 3 4 5 6 7 06H CS# SCLK SI SO High-Z Command 0 1 2 3 4 5 6 7 04H CS# SCLK SI SO High-Z |
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