Datenblatt-Suchmaschine für elektronische Bauteile |
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GD25B257D Datenblatt(PDF) 31 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B257D Datenblatt(HTML) 31 Page - GigaDevice Semiconductor (Beijing) Inc. |
31 / 92 page 3.3V Uniform Sector Dual and Quad Serial Flash GD25B257D 31 8.11. Quad Output Fast Read (QOFR 6BH or 4QOFR 6CH) The Quad Output Fast Read command is followed by 3-Byte address (A23-A0) and a dummy Byte, and each bit being latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown below. The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte of data is shifted out. Figure 19. Quad Output Fast Read Sequence Diagram (ADS=0) Command 0 1 2 3 4 5 6 7 6BH CS# SCLK SI(IO0) SO(IO1) High-Z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24-bit address 34 35 36 37 33 1 5 1 5 1 5 1 38 39 Byte1 32 42 43 44 45 41 46 47 40 5 Dummy Clocks 0 4 0 4 0 4 0 4 4 5 IO2 High-Z IO3 High-Z CS# SCLK SI(IO0) SO(IO1) IO2 IO3 2 6 2 6 2 6 2 6 6 3 7 3 7 3 7 3 7 7 Byte2 Byte3 Byte4 |
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