LOGIC DIAGRAM

VCCO

D3

D2

VEE

D1

D0

EN

26

27

28

2

3

4

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

5

6

7

8

9

10

Q3b

Q3a

Q3b

Q3a VCCO Q2b

Q2a

Q2b

Q2a

VCC

Q1b

Q1a

Q1b

Q1a

NC

VCCO Q0a

Q0b

Q0a

Q0b VCCO

D0

D1

D2

D3

EN

Q0a

Q0b

Q0a

Q0b

Q1a

Q1b

Q1a

Q1b

Q2a

Q2b

Q2a

Q2b

Q3a

Q3b

Q3a

Q3b

1

Pinout: 28-Lead PLCC (Top View)

* All VCC and VCCO pins are tied together on the die.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2–1

REV 2

12/93

Quad Driver

The MC10E/100E112 is a quad driver with two pairs of OR/NOR

outputs from each gate, and a common, buffered enable input. Using the

data inputs the device can serve as an ECL memory address fan-out

driver. Using just the enable input, the device serves as a clock driver,

although the MC10E/100E111 is designed specifically for this purpose,

and offers lower skew than the E112. For memory address driver

applications where scan capabilities are required, please refer to the

E212 device.

PIN NAMES

Pin

Function

D0 – D3

Data Inputs

EN

Enable Input

Qna, Qnb

True Outputs

Qna, Qnb

Inverting Outputs

MC10E112

MC100E112

QUAD DRIVER

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02