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LMS7002M Datenblatt(PDF) 14 Page - List of Unclassifed Manufacturers

Teilenummer LMS7002M
Bauteilbeschribung  FPRF MIMO Transceiver IC With Integrated Microcontroller
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LMS7002M
14
LMS7002M
– MIMO Multi-Band Multi-Standard
Transceiver IC
DACs ELECTRICAL SPECIFICATIONS
Parameter
Min.
Typ.
Max.
Unit
Condition
Digital Core Supply
1.1
1.2
1.3
V
Generated using integrated LDOs
Analog Supply
1.1
1.2
1.3
V
Generated using integrated LDOs
Number of Bits
12
bits
Two’s complement format
DAC Sampling Rate
640
MHz
Full Scale Current
625
uA
Programmable
SFDR
63
62
dBc
Fin=10MHz,-1dBFS
Fin=37MHz,-2dBFS
ENOB
9
bits
Table 8: DACs electrical specifications
ADCs ELECTRICAL SPECIFICATIONS
Parameter
Min.
Typ.
Max.
Unit
Condition
Digital Core Supply
1.1
1.2
1.3
V
Generated using integrated LDOs
Analog Supply
1.1
1.2
1.3
V
Generated using integrated LDOs
Number of Bits
12
bits
Two’s complement format
ADC Sampling Rate
160
MHz
Input Amplitude
0.8
Vpp
Differential
Input Common Mode Voltage
0.55
V
SFDR
63
62
dBc
Fin=10MHz,-1dBFS
Fin=37MHz,-2dBFS
ENOB
9
bits
Table 9: ADCs electrical specifications
SERIAL PORT INTERFACE
Description
The functionality of the LMS7002M transceiver is fully controlled by a
set of internal registers which can be accessed through a serial port
interface. Both write and read SPI operations are supported. The serial
port can be configured to run in 3 or 4 wire mode with the following pins
used:
SEN
serial port enable, active low
SCLK
serial clock, positive edge sensitive
SDIO
serial data in/out in 3 wire mode
serial data input in 4 wire mode
SDO
serial data out in 4 wire mode
don’t care in 3 wire mode
Serial port key features:
32 SPI clock cycles are required to complete a write operation.
32 SPI clock cycles are required to complete a read operation.
Multiple write/read operations are possible without toggling serial
port enable signal.
All configuration registers are 16-bit wide. Write/read sequence consists
of 16-bit instruction followed by 16-bit data to write or read. MSB of the
instruction bit stream is used as SPI command where CMD = 1 for write
and CMD = 0 for read. Next 4 bits are reserved (Reserved[3:0]) and
must be zeroes. Next 5 bits represent module address (Maddress[4:0])
since the LMS7002M configuration registers are divided into logical
blocks as shown in Table 11. The remaining 6 bits of the instruction are
used to address particular registers (Reg[5:0]) within the block.
Maddress and Reg compiles global 11-bit register address when
concatenated ((Maddress << 6) | Reg).
The write/read cycle waveforms are shown in Figure 42, Figure 43 and
Figure 44. Note that the write operation is the same for both 3-wire and
4-wire modes. Although not shown in the figures, multiple write/read is
possible by repeating the instruction/data sequence while keeping SEN
low.
SPI Timing Parameters
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency,
4-wire mode
3-wire mode
50
MHz
20
MHz
Enable Setup Time (tES)
2
ns
Enable Hold Time (©)
0.2
ns
Data Setup Time (tDS)
1
ns
Data Hold Time (tDH)
0.2
ns
Data Output Delay (tOD) at 12pF load
6
ns
Table 10: SPI timing parameters at 2.7V IO supply


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