Datenblatt-Suchmaschine für elektronische Bauteile |
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THGBMHG6C1LBAIL Datenblatt(PDF) 22 Page - Toshiba Semiconductor |
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THGBMHG6C1LBAIL Datenblatt(HTML) 22 Page - Toshiba Semiconductor |
22 / 33 page THGBMHG6C1LBAIL 22 Jul. 31th, 2015 Bus Timing Specification in HS200 mode HS200 Clock Timing Host CLK Timing in HS200 mode shall conform to the timing specified in following figure and Table. CLK input shall satisfy the clock timing over all possible operation and environment conditions. CLK input parameters should be measured while CMD and DAT lines are stable high or low, as close as possible to the Device. The maximum frequency of HS200 is 200MHz. Hosts can use any frequency up to the maximum that HS200 mode allows. NOTE 1 VIH denote VIH(min.) and VIL denotes VIL(max.). NOTE 2 VT = 50% of VCCQ, indicates clock reference point for timing measurements. Symbol Min Max Unit Remark tPERIOD 5 ns 200MHz (Max.), between rising edges tTLH, tTHL 0.2 * tPERIOD ns tTLH, tTHL < 1ns (max.) at 200MHz, CDEVICE=6pF, The absolute maximum value of tTLH, tTHL is 10ns regardless of clock frequency. Duty Cycle 30 70 % HS200 Device Input Timing NOTE 1 tISU and tIH are measured at VIL(max) and VIH(min). NOTE 2 VIH denote VIH(min) and VIL denotes VIL(max). Symbol Min Max Unit Remark tISU 1.40 ns CDEVICE ≤ 6pF tIH 0.8 ns CDEVICE ≤ 6pF VIH VIL VT tTLH tPERIOD tTHL VCCQ VSS CLOCK INPUT VT tPERIOD VCCQ VSS CLOCK INPUT VIH VIL tISU tIH CMD.DAT[7-0] INPUT VALID WINDOW VIH VIL VCCQ VSS |
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