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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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LT8920 Datenblatt(PDF) 45 Page - List of Unclassifed Manufacturers |
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LT8920 Datenblatt(HTML) 45 Page - List of Unclassifed Manufacturers |
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45 / 51 page  LT8920 Datasheet V1.1 Page 45 Jan. 2017 11.9. Crystal Oscillator The LT8910 supports quartz crystal, or external clock input. 11.9.1. Quartz crystal application Series resistor R2 limits power to the crystal, and contributes to the phase shift necessary for oscillation. Crystal loading capacitors C7 and C8 largely determine the load seen by the crystal, which should match the crystal vendor’s specification. These capacitor values can be trimmed, to fine-tune the frequency of oscillation. Self- bias resistor R1, from buffer output to input, serves to self-bias the on-chip buffer to the center of the linear region for maximum gain. 11.9.2. External clock application Self-bias resistor R1 should still be used, but the external clock may be coupled to the XTALI pin via a series DC blocking capacitor. See circuit below. Output resistor R0 is used to sample a small amount of power from an existing oscillator or clock circuit. The best value of R0 may need to be determined experimentally, but around 3k Ohms is a good starting point. In the extreme case of R0 being much too large, the RFIC will fail to initialize to the IDLE state properly. Regarding PCB layout: The CLK trace should be kept short and direct. The trace should be relatively narrow (high impedance), and must route away from other traces on the PCB that may inject or couple noise onto the CLK trace. The LT8910 will receive the clock signal relative to ground; therefore, the ground between chips should be a good low-noise, low-inductance ground. Ideally, this GND return should be a single ground plane on the PCB layout. Figure 17. External Clock Application LT8910 MCU MCU Digital Interface Rs C2 Crystal C1 Rf Ro Cc GND GND Rf CLK Test Point To Freq. Counter Additional Notes: 1. Clock duty cycle should be 50%. If not 50%, some additional drive voltage may be required (i.e. reduce R0). 2. If received Bit Error Rate (BER) is high, it can be caused by insufficient clock drive to the RFIC (i.e. reduce R0). 3. Another cause for high BER is phase noise on the clock signal. Try putting 0.1 and 2.2 uF ceramic bypass capacitors across |
Ähnliche Teilenummer - LT8920 |
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Ähnliche Beschreibung - LT8920 |
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