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MC100E256 Datenblatt(PDF) 1 Page - ON Semiconductor |
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MC100E256 Datenblatt(HTML) 1 Page - ON Semiconductor |
1 / 5 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 2–1 REV 2 © Motorola, Inc. 1996 12/93 3Bit 4:1 MuxLatch The MC10E/100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs (see logic symbol). When the Latch Enable (LEN) is LOW, the latch is transparent, and output data is controlled by the multiplexer select controls. A logic HIGH on LEN latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. • 950ps Max. D to Output • 850ps Max. LEN to Output • Split Select • Differential Outputs • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors SEL1A SEL1B SEL2 VEE LEN MR D1c 26 27 28 2 3 4 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 5 6 7 8 9 10 D1b D1a D2d D2c D2b D2a VCCO Q2 Q2 VCC Q1 Q1 VCCO Q0 D1d D0a D0b D0c D0d VCCO Q0 1 Pinout: 28-Lead PLCC (Top View) * All VCC and VCCO pins are tied together on the die. FUNCTION TABLE Pin State Operation SEL2 H Output c/d Data SEL1A H Input d Data SEL1B H Input b Data PIN NAMES Pin Function D0x – D2x Data Inputs SEL1A, SEL1B First-stage Select Inputs SEL2 Second-stage Select input LEN Latch Enable MR Master Reset Q0, Q0 – Q2, Q2 Data Outputs MC10E256 MC100E256 3-BIT 4:1 MUX-LATCH FN SUFFIX PLASTIC PACKAGE CASE 776-02 |
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