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CAT1022WE-28TE13 Datenblatt(PDF) 10 Page - Catalyst Semiconductor |
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CAT1022WE-28TE13 Datenblatt(HTML) 10 Page - Catalyst Semiconductor |
10 / 20 page 10 CAT1021, CAT1022, CAT1023 Doc. No. 3009, Rev. K ACKNOWLEDGE After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. All devices respond with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. When a device begins a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the device will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/ W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends a 8-bit address that is to be written into the address pointers of the device. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The device acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to non-volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. Figure 7. Slave Address Bits CAT Default Configuration 1 010 0 0 0 R/W START BIT SDA STOP BIT SCL Figure 5. Start/Stop Timing ACKNOWLEDGE 1 START SCL FROM MASTER 89 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER Figure 6. Acknowledge Timing |
Ähnliche Teilenummer - CAT1022WE-28TE13 |
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Ähnliche Beschreibung - CAT1022WE-28TE13 |
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