MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2–233

REV 5

3/93

16 x 4 Bit Register File (RAM)

The MC10H145 is a 16 x 4 bit register file. The active-low chip select allows

easy expansion.

The operating mode of the register file is controlled by the WE input. When

WE is “low” the device is in the write mode, the outputs are “low” and the data

present at Dn input is stored at the selected address, when WE is “high,” the

device is in the read mode — the data state at the selected location is present

at the Qn outputs.

• Address Access Time, 4.5 ns Typical

• Power Dissipation, 700 mW Typical

• Improved Noise Margin 150 mV (Over Operating Voltage and

Temperature Range)

• Voltage Compensated

• MECL 10K-Compatible

MAXIMUM RATINGS

Characteristic

Symbol

Rating

Unit

Power Supply (VCC = 0)

VEE

–8.0 to 0

Vdc

Input Voltage (VCC = 0)

VI

0 to VEE

Vdc

Output Current — Continuous

— Surge

Iout

50

100

mA

Operating Temperature Range

TA

0 to +75

°C

Storage Temperature Range — Plastic

— Ceramic

Tstg

–55 to +150

–55 to +165

°C

ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)

Characteristic

Symbol

0

°

25

°

75

°

Unit

Characteristic

Symbol

Min

Max

Min

Max

Min

Max

Unit

Power Supply Current

IE

—

160

—

163

—

165

mA

Input Current High

IinH

—

375

—

220

—

220

µA

Input Current Low

IinL

0.5

—

0.5

—

0.3

—

µA

High Output Voltage

VOH

–1.02

–0.84

–0.98

–0.81

–0.92

–0.735

Vdc

Low Output Voltage

VOL

–1.95

–1.63

–1.95

–1.63

–1.95

–1.60

Vdc

High Input Voltage

VIH

–1.17

–0.84

–1.13

–0.81

–1.07

–0.735

Vdc

Low Input Voltage

VIL

–1.95

–1.48

–1.95

–1.48

–1.95

–1.45

Vdc

NOTE:

Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,

after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed

circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through

a 50-ohm resistor to –2.0 volts.

MC10H145

DIP

PIN ASSIGNMENT

Q1

Q0

CS

D1

D0

A3

A2

VEE

VCC

Q2

Q3

WE

D3

D2

A0

A1

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

TRUTH TABLE

MODE

INPUT

OUTPUT

CS

WE

Dn

Write “0”

L

X

Qn

Write “1”

Read

Disabled

L

L

H

L

L

L

H

X

X

L

L

H

L

Q

Q-State of Addressed Cell

L SUFFIX

CERAMIC PACKAGE

CASE 620–10

P SUFFIX

PLASTIC PACKAGE

CASE 648–08

FN SUFFIX

PLCC

CASE 775–02

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion

Tables on page 6–11 of the Motorola MECL Data

Book (DL122/D).