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MSP430FG4619 Datenblatt(PDF) 57 Page - Texas Instruments

Teilenummer MSP430FG4619
Bauteilbeschribung  MSP430FG461x, MSP430CG461x Mixed-Signal Microcontrollers
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Hersteller  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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MSP430FG4619 Datenblatt(HTML) 57 Page - Texas Instruments

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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
www.ti.com
SLAS508K – APRIL 2006 – REVISED MAY 2020
Submit Documentation Feedback
Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619
MSP430CG4618 MSP430CG4617 MSP430CG4616
Detailed Description
Copyright © 2006–2020, Texas Instruments Incorporated
6.9.8
Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3-pin or 4-pin), I2C, and asynchronous communication protocols like
UART, enhanced UART with automatic baudrate detection, and IrDA.
The USCI_A0 module provides support for SPI (3-pin or 4-pin), UART, enhanced UART and IrDA.
The USCI_B0 module provides support for SPI (3-pin or 4-pin) and I2C.
6.9.9
USART1
The hardware universal synchronous/asynchronous receive transmit (USART) peripheral module is used
for serial data communication. The USART supports synchronous SPI (3-pin or 4-pin) and asynchronous
UART communication protocols, using double-buffered transmit and receive channels.
6.9.10 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16,
16×8, 8×16, and 8×8 bit operations. The module supports signed and unsigned multiplication as well as
signed and unsigned multiply-and-accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles
are required.
6.9.11 Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-6. Timer_A3 Signal Connections
INPUT PIN NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
MODULE BLOCK
MODULE OUT
SIGNAL
OUTPUT PIN
NUMBER
PZ, ZCA, ZQW
PZ, ZCA, ZQW
82/B9 - P1.5
TACLK
TACLK
Timer
NA
ACLK
ACLK
SMCLK
SMCLK
82/B9 - P1.5
TACLK
INCLK
87/A7 - P1.0
TA0
CCI0A
CCR0
TA0
87/A7 - P1.0
86/E7 - P1.1
TA0
CCI0B
DVSS
GND
DVCC
VCC
85/D7 - P1.2
TA1
CCI1A
CCR1
TA1
85/D7 - P1.2
CAOUT (internal)
CCI1B
ADC12 (internal)
DVSS
GND
DVCC
VCC
79/A10 - P2.0
TA2
CCI2A
CCR2
TA2
79/A10 - P2.0
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC


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