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TLIN1028-Q1

SLLSEX4 – AUGUST 2019

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Copyright © 2019, Texas Instruments Incorporated

12 Layout

PCB design should start with design of the protection and filtering circuitry because ESD and EFT have a wide

frequency bandwidth from approximately 3 MHz to 3 GHz, high frequency layout techniques must be applied

during PCB design. Placement at the connector also prevents these noisy events from propagating further into

the PCB and system.

12.1 Layout Guidelines

•

to the device as possible.

•

Pin 2 (EN): EN is an input pin that is used to place the device in a low power sleep mode. If this feature is not

used, the pin should be pulled high to the regulated voltage supply of the microprocessor through a series

resistor, values between 1 k

Ω and 10 kΩ. Additionally, a series resistor may be placed on the pin to limit

current on the digital lines in the event of an over voltage fault.

•

Pin 3 (GND): This is the ground connection for the device. This pin should be tied to the ground plane

through a short trace with the use of two vias to limit total return inductance.

•

Pin 4 (LIN): This pin connects to the LIN bus. For slave applications, a 200 pF capacitor to ground is

implemented. For master applications, an additional series resistor and blocking diode should be placed

•

Pin 5 (RXD): The pin is an open drain output and requires and external pull-up resistor in the range of 1 k

Ω

to 10 k

Ω to function properly. If the microprocessor paired with the transceiver does not have an integrated

pull-up resistor value can be used to reduce standby current.

•

Pin 6 (TXD): The TXD pin is the transmit input signal to the device from the processors. A series resistor can

be placed to limit the input current to the device in the event of an over voltage on this pin. A capacitor to

ground can be placed close to the input pin of the device to filter noise.

•

Pin 7 (nRST): This pin connects to the processors as a reset out.

•

NOTE

All ground and power connections should be made as short as possible and use at least

two vias to minimize the total loop inductance.