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MC10H121FN Datenblatt(PDF) 1 Page - ON Semiconductor |
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MC10H121FN Datenblatt(HTML) 1 Page - ON Semiconductor |
1 / 4 page © Semiconductor Components Industries, LLC, 2000 May, 2000 – Rev. 7 1 Publication Order Number: MC10H121/D MC10H121 4-Wide OR-AND/OR-AND Gate The MC10H121 is a basic logic building block providing the simultaneous OR–AND/OR–AND–Invert function, useful in data control and digital multiplexing applications. This MECL 10H part is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in propagation delay, and no increase in power– supply current. • Propagation Delay, 1.0 ns Typical • Power Dissipation 100 mW/Gate Typical (same as MECL 10K) • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K–Compatible LOGIC DIAGRAM DIP PIN ASSIGNMENT VCC1 AOUT AOUT A1IN A1IN A1IN A2IN VEE VCC2 A4IN A4IN A4IN A3IN A3IN A2IN, A3IN A2IN 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 15 14 13 12 11 10 9 7 2 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 6 5 4 3 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). http://onsemi.com Device Package Shipping ORDERING INFORMATION MC10H121L CDIP–16 25 Units/Rail MC10H121P PDIP–16 25 Units/Rail MC10H121FN PLCC–20 46 Units/Rail MARKING DIAGRAMS 1 16 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week CDIP–16 L SUFFIX CASE 620A MC10H121L AWLYYWW PDIP–16 P SUFFIX CASE 648 PLCC–20 FN SUFFIX CASE 775 10H121 AWLYYWW 1 1 16 MC10H121P AWLYYWW |
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