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TDA9965 Datenblatt(PDF) 9 Page - NXP Semiconductors |
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TDA9965 Datenblatt(HTML) 9 Page - NXP Semiconductors |
9 / 22 page 2004 Jul 05 9 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 Note 1. Noise and clamp behaviour are not guaranteed for a PGA gain higher than 30 dB. DNL differential non linearity ramp input −±0.5 ±0.9 LSB td(s) sampling delay see Fig.5 −− 5ns Total chain characteristics (CTH + PGA + ADC) td(SHD-CLKADC) delay between SHD and CLKADC Vi(IN) = 1000 mV; transition (99%) in 1 pixel; code fco(CTH) = 0000; code GPGA = 128; see Fig.5 − 13 − ns th(SHD-CLKADC) SHD hold time compared to CLKADC Vi(IN) =32mV; transition (99%) in 1 pixel; code fco(CTH) = 0000; code GPGA = 767; see Fig.5 − 0 − ns Ntot(rms) total noise from CTH input to ADC output (RMS value) GPGA = 0 dB; code fco(CTH) = 0000 − 0.85 − LSB GPGA =30dB; code fco(CTH) = 0000; note 1 − 6 − LSB OCCD(max) maximum offset voltage between CCD floating level and CCD dark pixel level see Fig.11 −200 − +200 mV Vn(i)(eq)(rms) equivalent input noise (RMS value) GPGA =30dB; code fco(CTH) = 0000; note 1 − 90 −µV Digital outputs (fpix = 30 MHz; CL =10pF) VOH HIGH-level output voltage IOH = −1mA VCCO − 0.5 − VCCO V VOL LOW-level output voltage IOL = 1 mA 0 − 0.5 V th(o) output hold time see Fig.5 10 −− ns td(o) output delay VCCO = 5.25 V − 20 25 ns VCCO =3V − 26 31 ns VCCO = 2.5 V − 30 35 ns Serial interface fSCLK(max) maximum clock frequency of serial interface 5 −− MHz SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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Ähnliche Beschreibung - TDA9965 |
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