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IDT82V1054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE

INDUSTRIAL TEMPERATURE

LREG4: Channel I/O Data, Read/Write (03H/83H)

The Channel I/O Data bits contain the information of the SLIC I/O pins (SI1, SI2, SB1, SB2, SB3, SO1 and SO2) of the corresponding

channel.

If SB1, SB2 and SB3 are configured as outputs, data can only be written to them by global registers GREG10, GREG11 and GREG12

respectively, and not by this register.

LREG5: Transmit Timeslot and Transmit Highway Selection, Read/Write (04H/84H)

The Transmit Time Slot Bits TT[6:0] select a time slot (compressed code) or a time slot group (linear code) for the corresponding channel

to transmit the PCM data. The valid value is from 0 to 127(d), corresponding to TS0 to TS127. The default value of TT[6:0] is N for

Channel N+1 (N = 0 to 3).

The Transmit Highway Selection bit THS selects a PCM highway for the corresponding channel to transmit the PCM data.

THS = 0:

DX1 is selected (default);

THS = 1:

DX2 is selected.

LREG6: Receive Timeslot and Receive PCM Highway Selection, Read/Write (05H/85H)

The Receive Time Slot Bits RT[6:0] select a time slot (compressed code) or a time slot group (linear code) for the corresponding channel

to receive the PCM data. The valid value is from 0 to 127(d), corresponding to TS0 to TS127. The default value of RT[6:0] is N for

Channel N+1 (N = 0 to 3).

The Receive Highway Selection bit RHS selects a PCM highway for the corresponding channel to receive the PCM data.

RHS = 0:

DR1 is selected (default);

RHS = 1:

DR2 is selected.

LREG7: PCM Data Low Byte, Read Only (06H)

This register is used for MCU to monitor the transmit (A to D) PCM data. For linear code, this register contains the low byte of the

transmit PCM data and LREG8 contains the high byte of the transmit PCM data. For compressed code (A/µ-Law), this register contains

total 8 bits of the transmit PCM data.

The low byte or total 8 bits of transmit PCM data will be read out by applying a read command to this register, and at the same time, it will

be transmitted to the PCM highway without any interference.

LREG8: PCM Data High Byte, Read Only (07H)

b7

b6

b5

b4

b3

b2

b1

b0

Command

R/W

0

0000

11

I/O data

Reserved

SO2

SO1

SB3

SB2

SB1

SI2

SI1

b7

b6

b5

b4

b3

b2

b1

b0

Command

R/W

0

0001

00

I/O data

THS

TT[6]

TT[5]

TT[4]

TT[3]

TT[2]

TT[1]

TT[0]

b7

b6

b5

b4

b3

b2

b1

b0

Command

R/W

0

0001

01

I/O data

RHS

RT[6]

RT[5]

RT[4]

RT[3]

RT[2]

RT[1]

RT[0]

b7

b6

b5

b4

b3

b2

b1

b0

Command

00

0001

10

I/O data

PCM[7]

PCM[6]

PCM[5]

PCM[4]

PCM[3]

PCM[2]

PCM[1]

PCM[0]

b7

b6

b5

b4

b3

b2

b1

b0

Command

00

0001

11

I/O data

PCM[15]

PCM[14]

PCM[13]

PCM[12]

PCM[11]

PCM[10]

PCM[9]

PCM[8]