Datenblatt-Suchmaschine für elektronische Bauteile |
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CD1865 Datenblatt(PDF) 10 Page - Intel Corporation |
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CD1865 Datenblatt(HTML) 10 Page - Intel Corporation |
10 / 150 page CD1865 — Intelligent Eight-Channel Communications Controller 10 Datasheet 1.0 Overview The CD1865 is a cost-effective controller capable of controlling eight full-duplex channels transferring data at rates up to 115.2 kbps. The advantage of the CD1865 lies in its ability to efficiently move data from the serial channels to the host. This results in an order-of-magnitude improvement in system-level throughput and a reduction in overhead on the host CPU. To increase the overall data throughput of the system, the device relies on a combination of features. Most important are the buffers for transmit and receive data. Each serial channel has three 8-byte FIFOs — one each for transmit, receive, and receive exception status. The receive FIFOs have programmable thresholds to minimize interrupt latency requirements. The CD1865 is based on a high-performance proprietary RISC processor architecture developed by Intel specifically for data communication applications. This processor executes all instructions in one clock cycle, and uses a register-window architecture to ensure zero-overhead context switch for each type of internal interrupt. The CD1865 is fabricated in an advanced CMOS process. The device’s high throughput, low- power consumption, and high-level of integration permit system designs with minimum parts count, maximum performance, and maximum reliability. 1.1 Theory of Operation The CD1865 custom RISC processor is assisted by specialized peripheral logic. Serial data transmission and reception is handled by ‘bit engines’. Each channel has a bit engine for transmit and another for receive. While each engine handles all bit-level timing, bit-to-character assembly is done in firmware. Bits are passed to the processor by internal interrupts, over a special bus dedicated to this purpose. To reduce internal interrupts to zero, special interrupt context hardware points to the correct register window for every possible context. A unique Global Index register eliminates address calculations by always pointing to the current channel. The processor assembles bits into characters, checks parity and other formatting parameters, and stores the data in the FIFOs as required. FIFOs are maintained as RAM-based structures. Both the local processor and the host access them by Pointer registers, in effect an Indexed Addressing mode. The CD1865 communicates with the host by service requests and service acknowledgments. Service requests can be detected by interrupt lines or by on-device registers. Regardless of the method used, the CD1865 has features to minimize both the number of requests to be serviced and the time required to service them. FIFOs help reduce the number of service requests to one every eight characters. To reduce the time required per request, the CD1865 supplies separate vectors for four different types of service requests. This reduces the time required by the processor to effect the proper operation. For instance, there is a unique vector for ‘good data’, so that the host wastes no time checking status bits or error conditions. If there is an error condition, the CD1865 supplies a unique vector pointing to the error-handling routine. Other vectors report transmit status and modem signal change. Interrupts can be acknowledged either by an Interrupt Acknowledge pin, or by reading an on- device register. This allows host software maximum flexibility and speed in handling service requests. |
Ähnliche Teilenummer - CD1865 |
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Ähnliche Beschreibung - CD1865 |
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