Datenblatt-Suchmaschine für elektronische Bauteile |
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FIN24ACMLX Datenblatt(PDF) 4 Page - Fairchild Semiconductor |
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FIN24ACMLX Datenblatt(HTML) 4 Page - Fairchild Semiconductor |
4 / 21 page www.fairchildsemi.com 4 Control Logic Circuitry The FIN24AC has the ability to be used as a 24-bit Serializer or a 24-bit Deserializer. Pins S1 and S2 must be set to accommo- date the clock reference input frequency range of the serializer. The table below shows the pin programming of these options based on the S1 and S2 control pins. The DIRI pin controls whether the device is a serializer or a deserializer. When DIRI is asserted LOW, the device is configured as a deserializer. When the DIRI pin is asserted HIGH, the device will be configured as a serializer. Changing the state on the DIRI signal will reverse the direction of the I/O signals and generate the opposite state sig- nal on DIRO. For unidirectional operation the DIRI pin should be hardwired to the HIGH or LOW state and the DIRO pin should be left floating. For bi-directional operation the DIRI of the mas- ter device will be driven by the system and the DIRO signal of the master will be used to drive the DIRI of the slave device. Serializer/Deserializer with Dedicated I/O Variation The serialization and deserialization circuitry is setup for 24 bits. Because of the dedicated inputs and outputs only 22 bits of data are ever serialized or deserialized. Regardless of the mode of operation the serializer is always sending 24 bits of data plus 2 boundary bits and the deserializer is always receiving 24 bits of data and 2 word boundary bits. Bits 23 and 24 of the serializer will always contain the value of zero and will be discarded by the deserializer. DP[21:22] input to the serializer will be deseri- alized to DP[23:24] respectively. Turn-Around Functionality The device passes and inverts the DIRI signal through the device asynchronously to the DIRO signal. Care must be taken by the system designer to insure that no contention occurs between the deserializer outputs and the other devices on this port. Optimally the peripheral device driving the serializer should be put into a HIGH Impedance state prior to the DIRI sig- nal being asserted. When a device with dedicated data outputs turns from a deseri- alizer to a serializer the dedicated outputs will remain at the last logical value asserted. This value will only change if the device is once again turned around into a deserializer and the values are overwritten. TABLE 1. Control Logic Circuitry Power-Down Mode: (Mode 0) Mode 0 is used for powering down and resetting the device. When both of the mode signals are driven to a LOW state the PLL and references will be disabled, differential input buffers will be shut off, differential output buffers will be placed into a HIGH impedance state, LVCMOS outputs will be placed into a HIGH impedance state and LVCMOS inputs will be driven to a valid level internally. Additionally all internal circuitry will be reset. The loss of CKREF state is also enabled to insure that the PLL will only power-up if there is a valid CKREF signal. In a typical application mode signals of the device will typically not change states other than between the desired frequency range and the power-down mode. This allows for system level power-down functionality to be implemented via a single wire for a SerDes pair. The S1 and S2 selection signals that have their operating mode driven to a “logic 0” should be hardwired to GND. The S1 and S2 signals that have their operating mode driven to a “logic 1” should be connected to a system level power-down signal. Serializer Operation Mode The serializer configurations are described in the following sec- tions. The basic serialization circuitry works essentially identi- cally in these modes, but the actual data and clock streams will differ depending on if CKREF is the same as the STROBE sig- nal or not. When it is stated that CKREF = STROBE this means that the CKREF and STROBE signals have an identical fre- quency of operation but may or may not be phase aligned. When it is stated that CKREF does not equal STROBE then each signal is distinct and CKREF must be running at a fre- quency high enough to avoid any loss of data condition. CKREF must never be a lower frequency than STROBE. Serializer Operation: (Figure 1) Modes 1, 2, or 3 DIRI equals 1 CKREF equals STROBE The PLL must receive a stable CKREF signal in order to achieve lock prior to any valid data being sent. The CKREF sig- nal can be used as the data STROBE signal provided that data can be ignored during the PLL lock phase. Once the PLL is stable and locked the device can begin to cap- ture and serialize data. Data will be captured on the rising edge of the STROBE signal and then serialized. The serialized data stream is synchronized and sent source synchronously with a bit clock with an embedded word boundary. When operating in this mode the internal deserializer circuitry is disabled including the serial clock, serial data input buffers, the bi-directional paral- lel outputs and the CKP word clock. The CKP word clock will be driven HIGH. Serializer Operation: (Figure 2) DIRI equals 1 CKREF does not equal STROBE If the same signal is not used for CKREF and STROBE, then the CKREF signal must be run at a higher frequency than the STROBE rate in order to serialize the data correctly. The actual serial transfer rate will remain at 26 times the CKREF fre- quency. A data bit value of zero will be sent when no valid data Mode Number S2 S1 DIRI Description 0 0 0 x Power-Down Mode 1 0 1 1 24-Bit Serializer 2MHz to 5MHz CKREF 0 1 0 24-Bit Deserializer 2 1 0 1 24-Bit Serializer 5MHz to 15MHz CKREF 1 0 0 24-Bit Deserializer 3 1 1 1 24-Bit Serializer 10MHz to 20MHz CKREF 1 1 0 24-Bit Deserializer |
Ähnliche Teilenummer - FIN24ACMLX |
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Ähnliche Beschreibung - FIN24ACMLX |
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