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74LVXZ161284MEA Datenblatt(PDF) 2 Page - Fairchild Semiconductor |
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74LVXZ161284MEA Datenblatt(HTML) 2 Page - Fairchild Semiconductor |
2 / 11 page www.fairchildsemi.com 2 Logic Symbol Connection Diagram Pin Descriptions Truth Table Note 1: Y9–Y13 Open Drain Outputs with 1.4 kΩ pullups Note 2: B1–B8 Open Drain Outputs with 1.4 kΩ pullups Pin Names Description HD High Drive Enable Input (Active HIGH) DIR Direction Control Input A1–A8 Inputs or Outputs B1–B8 Inputs or Outputs A9–A13 Inputs Y9–Y13 Outputs A14–A17 Outputs C14–C17 Inputs PLHIN Peripheral Logic HIGH Input PLH Peripheral Logic HIGH Output HLHIN Host Logic HIGH Input HLH Host Logic HIGH Output Inputs Outputs DIR HD LL B1–B8 Data to A1–A8, and A9–A13 Data to Y9–Y13 (Note 1) C14–C17 Data to A14–A17 PLH Open Drain Mode LH B1–B8 Data to A1–A8, and A9–A13 Data to Y9–Y13 C14–C17 Data to A14–A17 HL A1–A8 Data to B1–B8 (Note 2) A9–A13 Data to Y9–Y13 (Note 1) C14–C17 Data to A14–A17 PLH Open Drain Mode HH A1–A8 Data to B1–B8 A9–A13 Data to Y9–Y13 C14–C17 Data to A14–A17 |
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