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74ABTH16899 Datenblatt(PDF) 7 Page - NXP Semiconductors |
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74ABTH16899 Datenblatt(HTML) 7 Page - NXP Semiconductors |
7 / 16 page Philips Semiconductors Product specification 74ABT16899 74ABTH16899 18-bit latched transceiver with 16-bit parity generator/checker (3-State) 1998 Feb 25 7 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Tamb = –40°C to +85 °C UNIT Min Typ Max Min Max VIK Input clamp voltage VCC = 4.5V; IIK = –18mA –0.7 –1.2 –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 3.1 2.5 V VOH High-level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.6 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.7 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.36 0.55 0.55 V VRST Power-up output low voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V II Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.2 ±1.0 ±1.0 µA current Data pins VCC = 5.5V; VI = GND or 5.5V ±1.0 ±100 ±100 µA Bushold current A or B VCC = 4.5V; VI = 0.8V 75 75 IHOLD Bushold current A or B inputs5 74ABTH16899 VCC = 4.5V; VI = 2.0V –75 –75 µA 74ABTH16899 VCC = 5.5V; VI = 0 to 5.5V ±500 IOFF Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±2.0 ±100 ±100 µA IPU/IPD Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.5V; VI = GND or VCC ±5.0 ±50 ±50 µA IIH + IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 2.0 50 50 µA IIL + IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –2.0 –50 –50 µA ICEX Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 2.0 50 50 µA IO Output current1 VCC = 5.5V; VO = 2.5V –50 –100 –180 –50 –180 mA ICCH VCC = 5.5V; Outputs High, VI = GND or VCC 0.5 1 1 mA ICCL Quiescent supply current VCC = 5.5V; Outputs Low, VI = GND or VCC 10.5 19 19 mA ICCZ VCC = 5.5V; Outputs 3-State; VI = GND or VCC 0.5 1 1 mA ∆ICC Additional supply current per input pin2 VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.2 1.5 1.5 mA NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10%, a transition time of up to 100 µsec is permitted. 5. This is the bus hold overdrive current required to force the input to the opposite logic state. |
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