Philips Semiconductors

Product specification

74ABT821

10-bit D-type flip-flop; positive-edge trigger

(3-State)

1995 Sep 06

5

AC SETUP REQUIREMENTS

LIMITS

SYMBOL

PARAMETER

WAVEFORM

UNIT

Min

Typ

Min

Setup time, High or Low

Dn to CP

2

2.1

2.1

0.5

0.3

2.1

2.1

ns

Hold time, High or Low

Dn to CP

2

1.3

1.3

0.0

–0.3

1.3

1.3

ns

CP pulse width

High or Low

1

2.9

3.8

1.8

2.8

2.9

3.8

ns

AC WAVEFORMS

VM

tPLH

tPHL

VM

VM

VM

CP

Qn

1/fMAX

tW(H)

tW(L)

SA00159

Waveform 1. Propagation Delay, Clock Input to Output, Clock

Pulse Width, and Maximum Clock Frequency

OE

0V

Qn

SA00066

Waveform 3. 3–State Output Enable Time to High Level and

Output Disable Time from High Level

Dn

CP

NOTE: The shaded areas indicate when the input is permitted

to change for predictable output performance.

SA00107

Waveform 2. Data Setup and Hold Times

OE

0V

Qn

SA00067

Waveform 4. 3–State Output Enable Time to Low Level and

Output Disable Time from Low Level