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74ABT821N Datenblatt(PDF) 1 Page - NXP Semiconductors |
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74ABT821N Datenblatt(HTML) 1 Page - NXP Semiconductors |
1 / 6 page Philips Semiconductors Product specification 74ABT821 10-bit D-type flip-flop; positive-edge trigger (3-State) 1 1995 Sep 06 853-1616 15703 FEATURES • High speed parallel registers with positive edge-triggered D-type flip-flops • Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model • Power-up 3-State • Power-up Reset DESCRIPTION The 74ABT821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT821 Bus interface Register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The 74ABT821 is a buffered 10-bit wide version of the 74ABT374/74ABT534 functions. The 74ABT821 is a 10-bit, edge triggered register coupled to ten 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates. The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all ten 3-State buffers independent of the register operation. When OE is Low, the data in the register appears at the outputs. When OE is High, the outputs are in high impedance ”off” state, which means they will neither drive nor load the bus. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V TYPICAL UNIT tPLH tPHL Propagation delay CP to Qn CL = 50pF; VCC = 5V 4.6 ns CIN Input capacitance VI = 0V or VCC 4 pF COUT Output capacitance Outputs disabled; VO = 0V or VCC 7 pF ICCZ Total supply current Outputs disabled; VCC =5.5V 500 nA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 24-Pin Plastic DIP –40 °C to +85°C 74ABT821 N 74ABT821 N SOT222-1 24-Pin plastic SO –40 °C to +85°C 74ABT821 D 74ABT821 D SOT137-1 24-Pin Plastic SSOP Type II –40 °C to +85°C 74ABT821 DB 74ABT821 DB SOT340-1 24-Pin Plastic TSSOP Type I –40 °C to +85°C 74ABT821 PW 74ABT821PW DH SOT355-1 PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21 22 23 24 OE D0 D1 D2 D3 D4 D5 D6 D7 Q7 D8 Q6 Q5 Q4 Q3 Q2 Q1 Q0 VCC Q8 11 14 D9 Q9 12 13 GND CP TOP VIEW SA00223 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1 OE Output enable input (active-Low) 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 D0-D9 Data inputs 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 Q0-Q9 Data outputs 13 CP Clock pulse input (active rising edge) 10 GND Ground (0V) 20 VCC Positive supply voltage |
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