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74AHCT1G79 Datenblatt(PDF) 2 Page - NXP Semiconductors |
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74AHCT1G79 Datenblatt(HTML) 2 Page - NXP Semiconductors |
2 / 12 page 1999 May 18 2 Philips Semiconductors Product specification Single D-type flip-flop; positive-edge trigger 74AHC1G79; 74AHCT1G79 FEATURES • Symmetrical output impedance • High noise immunity • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V; MM EIA/JESD22-A115-A exceeds 200 V • Low power dissipation • Balanced propagation delays • Very small 5 pin package • Output capability: standard. DESCRIPTION The 74AHC1G/AHCT1G79 is a high-speed Si-gate CMOS device. The 74AHC1G/AHCT1G79 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. FUNCTION TABLE See note 1. Note 1. H = HIGH voltage level; L = LOW voltage level; ↑ = LOW-to-HIGH CP transition; X = don’t care; Q + 1 = state after the next LOW-to-HIGH CP transition. INPUTS OUTPUT CP D Q+1 ↑ LL ↑ HH LX Q QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi +(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V. 2. The condition is VI = GND to VCC. PINNING SYMBOL PARAMETER CONDITIONS TYPICAL UNIT AHC1G AHCT1G tPHL/tPLH propagation delay CP to Q CL =15pF; VCC =5V 3.5 3.5 ns CI input capacitance 1.5 1.5 pF CPD power dissipation capacitance notes 1 and 2; CL =50pF; f = 1 Mhz 15 16 pF PIN SYMBOL DESCRIPTION 1 D data input 2 CP clock pulse input 3 GND ground (0 V) 4 Q data output 5VCC DC supply voltage |
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