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74AHCT74D Datenblatt(PDF) 2 Page - NXP Semiconductors

Teilenummer 74AHCT74D
Bauteilbeschribung  Dual D-type flip-flop with set and reset; positive-edge trigger
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Hersteller  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74AHCT74D Datenblatt(HTML) 2 Page - NXP Semiconductors

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1999 Sep 23
2
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74AHC74; 74AHCT74
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
• Balanced propagation delays
• Inputs accepts voltages higher than
VCC
• For AHC only:
operates with CMOS input levels
• For AHCT only:
operates with TTL input levels
• Output capability: standard
• ICC category: flip-flops
• Specified from
−40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT74 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
No. 7A.
The 74AHC/AHCT74 dual
positive-edge triggered, D-type
flip-flops with individual data (D)
inputs, clock (CP) inputs, set (SD) and
reset (RD) inputs; also
complementary Q and Q outputs.
The set and reset are asynchronous
active LOW inputs and operate
independently of the clock input.
Information on the data input is
transferred to the Q output on the
LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable
one set-up time prior to the
LOW-to-HIGH clock transition for
predictable operation.
Schmitt-trigger action in the clock
input makes the circuit highly tolerant
to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
FUNCTION TABLES
Table 1
See note 1
Table 2
See note 1
Note to Tables 1 and 2
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH CP transition;
Qn+1 = state after the next LOW-to-HIGH CP transition.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
tPHL/tPLH
propagation delay
CL = 15 pF;
VCC =5V
nCP to nQ, nQ
3.7
3.3
ns
nSD,nRD to nQ, nQ
3.7
3.7
ns
fmax
max. clock frequency
130
100
MHz
CI
input capacitance
VI =VCC or GND 4.0
4.0
pF
CPD
power dissipation
capacitance
CL = 50 pF;
f = 1 MHz;
notes 1 and 2
12
16
pF
INPUT
OUTPUT
nSD
nRD
nCP
nD
nQ
nQ
LH
X
X
HL
HL
X
X
LH
LL
X
X
H
H
INPUT
OUTPUT
nSD
nRD
nCP
nD
nQn+1
nQn+1
HH
LL
H
HH
HH
L


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