Philips Semiconductors

Product specification

74ALVT162823

2.5V/3.3V 18-bit bus-interface D-type flip-flop with reset

and enable with 30

Ω termination resistors (3-State)

2

1998 Aug 27

853-2114 19927

FEATURES

edge-triggered D-type flip-flops

required with MOS microprocessors

and 200 V per Machine Model

resistors to hold unused inputs

termination resistors unnecessary

DESCRIPTION

The 74ALVT162823 18-bit bus interface register is designed to

eliminate the extra packages required to buffer existing registers and

provide extra data width for wider data/address paths of buses

carrying parity.

The 74ALVT162823 has two 9-bit wide buffered registers with Clock

Enable (nCE) and Master Reset (nMR) which are ideal for parity bus

interfacing in high microprogrammed systems.

The registers are fully edge-triggered. The state of each D input, one

set-up time before the Low-to-High clock transition is transferred to

the corresponding flip-flop’s Q output.

The 74ALVT162823 is designed with 30

Ω series resistance in both

the pull-up and pull-down output structures. This design reduces line

noise in applications such as memory address drivers, clock drivers,

and bus receivers/transmitters.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

SYMBOL

PARAMETER

2.5V

3.3V

UNIT

Propagation delay

nCP to nQx

4.2

3.4

3.0

2.8

ns

Input capacitance

3

3

pF

Output capacitance

9

9

pF

Total supply current

Outputs disabled

40

70

µA

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

56-Pin Plastic SSOP Type III

–40

°C to +85°C

74ALVT162823 DL

AV162823 DL

SOT371–1

56-Pin Plastic TSSOP Type II

–40

°C to +85°C

74ALVT162823 DGG

AV162823 DGG

SOT364–1

PIN DESCRIPTION

PIN NUMBER

SYMBOL

FUNCTION

2, 27

1OE, 2OE

Output enable input (active-Low)

54, 52, 51, 49, 48, 47, 45, 44, 43

42, 41, 40, 38, 37, 36, 34, 33, 31

1D0-1D8

2D0-2D8

Data inputs

3, 5, 6, 8, 9, 10, 12, 13, 14

15, 16, 17, 19, 20, 21, 23, 24, 26

1Q0-1Q8

2Q0-2Q8

Data outputs

56, 29

1CP, 2CP

Clock pulse input (active rising edge)

55, 30

1CE, 2CE

Clock enable input (active-Low)

1, 28

1MR, 2MR

Master reset input (active-Low)

4, 11, 18, 25, 32, 39, 46, 53

GND

Ground (0V)

7, 22, 35, 50

Positive supply voltage