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YWW7640I Datenblatt(PDF) 7 Page - IC MICROSYSTEMS |
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YWW7640I Datenblatt(HTML) 7 Page - IC MICROSYSTEMS |
7 / 14 page X76F400 Characteristics subject to change without notice. 7 of 14 REV 1.0 7/5/00 www.icmic.com PASSWORDS Passwords are changed by sending the “change read password” or “change write password” commands in a normal sector write operation. A full 8 bytes containing the new password must be sent, following successful transmission of the current write password and a valid password ACK response. The user can use a repeated ACK polling command to check that a new password has been written correctly. An ACK indicates that the new password is valid. There is no way to read any of the passwords. RESPONSE-TO-RESET (DEFAULT = 19 40 AA 55) The ISO Response-to-reset is controlled by the RST and CLK pins. When RST is pulsed high during a clock pulse, the device will output 32 bits of data, one bit per clock, and it resets to the standby state. This conforms to the ISO standard for “synchronous response to reset.” The part must not be in a write cycle for the response-to-reset to occur. After initiating a nonvolatile write cycle, the RST pin must not be pulsed until the nonvolatile write cycle is complete. If not, the ISO response will not be activated. If the RST is pulsed HIGH and the CLK is within the RST pulse (meet the t NOL spec.) in the middle of an ISO transaction, it will output the 32 bit sequence again (starting at bit 0). Otherwise, this aborts the ISO operation and the part returns to standby state. If the RST is pulsed HIGH and the CLK is outside the RST pulse (in the middle of an ISO transaction), this aborts the ISO operation and the part returns to standby state. If power is interrupted during the response-to-reset, the response-to-reset will be aborted and the part will return to the standby state. A response-to-reset is not available during a nonvolatile write cycle. Figure 7. Response to RESET (RST) SCK SO RST Byte 0 MSB LSB LSB MSB 1 LSB MSB LSB MSB 2 3 10 0 00 11 1 0 0 1 0000 0 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 0 |
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