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YWW7640AF Datenblatt(PDF) 2 Page - IC MICROSYSTEMS

Teilenummer YWW7640AF
Bauteilbeschribung  Secure SerialFlash
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Hersteller  ICMIC [IC MICROSYSTEMS]
Direct Link  http://www.icmic.com
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YWW7640AF Datenblatt(HTML) 2 Page - IC MICROSYSTEMS

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X76F400
Characteristics subject to change without notice.
2 of 14
REV 1.0 7/5/00
www.icmic.com
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is an open drain serial data input/output pin. During a
read cycle, data is shifted out on this pin. During
a write cycle, data is shifted in on this pin. In all other
cases, this pin is in a high impedance state.
Reset (RST)
RST is a device reset pin. When RST is pulsed high, the
X76F400 will output 32 bits of fixed data, which
conforms to the standard for “synchronous response-
to-reset.” The part must not be in a write cycle for the
response-to-reset to occur. See Figure 7. If power is
interrupted during the response-to-reset, the response-
to-reset will be aborted and the part will return to the
standby state. The response to reset is “mask
programmable” only!
DEVICE OPERATION
The X76F400 memory array consists of 62 8-byte sectors.
Read or write access to the array always begins at
the first address of the sector. Read operations then can
continue indefinitely. Write operations must total 8 bytes.
There are two primary modes of operation for the
X76F400; Protected READ and protected WRITE. Pro-
tected operations must be performed with one of two 8- byte
passwords.
The basic method of communication for the device is
generating a start condition, then transmitting a com-
mand, followed by the correct password. All parts will be
shipped from the factory with all passwords equal to ‘0.’
The user must perform ACK polling to determine the
validity of the password, prior to starting a data transfer
(see Acknowledge Polling). Only after the correct password
is accepted, and an ACK polling has been
performed, can the data transfer occur. See Figure 1.
To ensure the correct communication, RST must
remain LOW under all conditions except when running
a “response-to-reset sequence”.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
If the X76F400 is in a nonvolatile write cycle a “no ACK”
(SDA = High) response will be issued in
response to loading of the command byte. If a stop is issued
prior to the nonvolatile write cycle, the write
operation will be terminated; the part will then reset and
enter into a standby mode.
(The basic sequence is illustrated in Figure 1.)
PIN NAMES
PIN CONFIGURATION
After each transaction is completed, the X76F400 will
reset and enter into a standby mode. This will also be
the response if an unsuccessful attempt is made to
access a protected array.
Symbol
Description
SDA
Serial Data Input/Output
SCL
Serial Clock Input
RST
Reset Input
VCC
Supply Voltage
VSS
Ground
NC
No Connect
SDA
VCC
RST
SCL
NC
1
2
3
4
7
8
6
5
SOIC
VSS
NC
NC
VSS
RST
SDA
NC
NC
1
2
3
4
7
8
6
5
VCC
SCL
NC
TSSOP


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