Datenblatt-Suchmaschine für elektronische Bauteile |
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MC100ES60T22DT Datenblatt(PDF) 1 Page - Freescale Semiconductor, Inc |
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MC100ES60T22DT Datenblatt(HTML) 1 Page - Freescale Semiconductor, Inc |
1 / 8 page MC100ES60T22 Rev 2, 2/2005 Freescale Semiconductor Technical Data © Freescale Semiconductor, Inc., 2005. All rights reserved. 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Translator The MC100ES60T22 is a low skew dual LVTTL/LVCMOS to differential LVPECL translator. The low voltage PECL levels, small package, and dual gate design are ideal for clock translation applications. Features • 280 ps typical propagation delay • 100 ps max output-to-output skew • LVPECL operating range: VCC = 3.135 V to 3.8 V • 8-lead SOIC and 8-lead TSSOP packages • Ambient temperature range –40°C to +85°C MC100ES60T22 D SUFFIX 8-LEAD SOIC PACKAGE CASE 751-06 ORDERING INFORMATION Device Package MC100ES60T22D SOIC-8 MC100ES60T22DR2 SOIC-8 MC100ES60T22DT TSSOP-8 MC100ES60T22DTR2 TSSOP-8 PIN DESCRIPTION Pin Function D0, D1 LVTTL/LVCMOS Inputs Qn, Qn LVPECL Differential Outputs VCC Positive Supply GND Negative Supply DT SUFFIX 8-LEAD TSSOP PACKAGE CASE 1640-01 Figure 1. 8-Lead Pinout (Top View) and Logic Diagram 1 2 3 45 6 7 8 D0 GND VCC Q0 D1 Q1 Q1 Q0 LVPECL LVTTL/LVCMOS |
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