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74HC534 Datenblatt(PDF) 2 Page - NXP Semiconductors

Teilenummer 74HC534
Bauteilbeschribung  Octal D-type flip-flop; positive edge-trigger; 3-state; inverting
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Hersteller  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74HC534 Datenblatt(HTML) 2 Page - NXP Semiconductors

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1998 Apr 10
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
FEATURES
• 3-state inverting outputs for bus oriented applications
• 8-bit positive, edge-triggered register
• Common 3-state output enable input
• Output capability: bus driver
• ICC category: MSI.
GENERAL DESCRIPTION
The 74HC/HCT534 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT534 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and inverting
3-state outputs for bus oriented applications. A clock (CP)
and an output enable (OE) input are common to all
flip-flops.
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition. When OE is LOW, the
contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The “534” is functionally identical to the “374”, but has
inverted outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf =6ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz.
fo = output frequency in MHz.
∑ (CL × VCC2 × fo) = sum of outputs.
CL = output load capacitance in pF.
VCC = supply voltage in V.
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay CP to Qn
CL = 15 pF; VCC =5V
12
13
ns
fmax
maximum clock frequency
61
40
MHz
CI
input capacitance
3.5
3.5
pF
CPD
power dissipation capacitance per flip-flop
notes 1 and 2
19
19
pF
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
74HC534
SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
74HC534
DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
74HCT534
SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
74HCT534
DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1


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