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74HCT74PW Datenblatt(PDF) 2 Page - NXP Semiconductors

Teilenummer 74HCT74PW
Bauteilbeschribung  Dual D-type flip-flop with set and reset; positive-edge trigger
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Hersteller  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74HCT74PW Datenblatt(HTML) 2 Page - NXP Semiconductors

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2003 Jul 10
2
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC74; 74HCT74
FEATURES
• Wide supply voltage range from 2.0 to 6.0 V
• Symmetrical output impedance
• High noise immunity
• Low power dissipation
• Balanced propagation delays
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
GENERAL DESCRIPTION
The 74HC/HCT74 is a high-speed Si-gate CMOS device
and is pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT74 are dual positive-edge triggered, D-type
flip-flops with individual data (D) inputs, clock (CP) inputs,
set (SD) and reset (RD) inputs; also complementary
Q and Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf =6ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. For 74HC74 the condition is VI = GND to VCC.
For 74HCT74 the condition is VI = GND to VCC − 1.5 V.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/tPLH
propagation delay
CL = 15 pF; VCC =5V
nCP to nQ, nQ14
15
ns
nSD to nQ, nQ15
18
ns
nRD to nQ, nQ16
18
ns
fmax
maximum clock frequency
76
59
MHz
CI
input capacitance
3.5
3.5
pF
CPD
power dissipation capacitance per flip-flop
notes 1 and 2
24
29
pF


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