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74LV423PW Datenblatt(PDF) 2 Page - NXP Semiconductors |
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74LV423PW Datenblatt(HTML) 2 Page - NXP Semiconductors |
2 / 16 page Philips Semiconductors Preliminary specification 74LV423 Dual retriggerable monostable multivibrator with reset 2 1997 Feb 04 853–1913 17724 FEATURES • Optimized for Low Voltage applications: 1.0 to 5.5V • Accepts TTL input levels between V CC = 2.7V and VCC = 3.6V • Typical V OLP (output ground bounce) t 0.8V @ VCC = 3.3V, Tamb = 25°C • Typical V OHV (output VOH undershoot) u 2V @ VCC = 3.3V, Tamb = 25°C • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long pulses up to 100% duty factor • Direct reset terminates output pulses • Schmitt-trigger action on all inputs except for the reset input • Output capability: standard (except for nR EXT/CEXT) • I CC category: MSI DESCRIPTION The 74LV423 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT423. The 74LV423 is a dual retriggerable monostable multivibrator with output pulse width control by three methods. The basic pulse time is programmed by selection of an external resistor (REXT) and capacitor (CEXT). They are normally connected as shown in Figure 1. Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as desired. Alternatively, an output delay can be terminated at any time by a LOW-going edge on input nRD, which also inhibits the triggering. Figures 2 and 3 illustrate pulse control by retriggering and early reset. The basic output pulse width is essentially determined by the values of the external timing components REXT and CEXT. For pulse width when CEXT <10000pF, see Figure 6. When CEXT u 10,000pF, the typical output pulse width is defined as: tW = 0.45 REXT CEXT (typ.), where tW = pulse width in ns; REXT = external resistor in KΩ; and CEXT = external capacitor in pF. Schmitt-trigger action in the nA and nB inputs makes the circuit highly tolerant of slower input rise and fall times. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf v2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay nA, nB to nQ, nQ nRD to nQ, nQ CL = 15pF VCC = 3.3V REXT = 5KΩ CEXT = 0pF 16 13 ns ns CI Input capacitance 3.5 pF CPD Power dissipation capacitance per flip-flop VCC = 3.3V, VI = GND to VCC1 17 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 fi )S (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL VCC2 fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 16-Pin Plastic DIL –40 °C to +125°C 74LV423 N 74LV423 N SOT38-1 16-Pin Plastic SO –40 °C to +125°C 74LV423 D 74LV423 D SOT109-1 16-Pin Plastic SSOP Type II –40 °C to +125°C 74LV423 DB 74LV423 DB SOT338-1 16-Pin Plastic TSSOP Type I –40 °C to +125°C 74LV423 PW 74LV423PW DH SOT403-1 |
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