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74LVC109DB Datenblatt(PDF) 6 Page - NXP Semiconductors |
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74LVC109DB Datenblatt(HTML) 6 Page - NXP Semiconductors |
6 / 10 page Philips Semiconductors Product specification 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger 1998 Apr 28 6 AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. SV00522 1/f max t h t h t PLH t PHL t PLH t PHL t W t su t su VM VM VM VM nJ, nK INPUT nCP INPUT nQ OUTPUT VI VI GND GND VOH VOH VOL VOL nQ OUTPUT Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ and nK to nCP set-up, the nCP to nJ, nK hold times and the maximum clock pulse frequency. SV00523 tW tW tPLH tPHL trem VM VM VM VM VM nSD INPUT nRD INPUT nCP INPUT nQ OUTPUT VOH Vl Vl Vl VOH VOL VOL GND GND GND nQ OUTPUT trem tPLH tPHL Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD, nSD to nCP removal time. TEST CIRCUIT VM VM tW NEGATIVE PULSE 10% 10% 90% 90% 0V VM VM tW VI POSITIVE PULSE 90% 90% 10% 10% 0V tTHL (tf) tTLH (tr)tTHL (tf) tTLH (tr) VM = 1.5V Input Pulse Definition SWITCH POSITION PULSE GENERATOR RT Vl D.U.T. VO CL RL Vcc RL Test Circuit for Outputs Open GND S1 DEFINITIONS VCC VI < 2.7V 2.7–3.6V VCC 2.7V TEST S1 tPLH/tPHL Open ≥ 4.5 V VCC RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance: See AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VI SV00904 2 < VCC Figure 3. Load circuitry for switching times. |
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