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MC100ES6130DT Datenblatt(PDF) 1 Page - Motorola, Inc |
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MC100ES6130DT Datenblatt(HTML) 1 Page - Motorola, Inc |
1 / 8 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order number: MC100ES6130 Rev 1, 5/2004 © Motorola, Inc. 2004 2.5/3.3V 1:4 PECL Clock Driver with 2:1 Input MUX The MC100ES6130 is a 2.5 GHz differential PECL 1:4 fanout buffer. The ES6130 offers a wide operating range of 2.5 V and 3.3 V and also features a 2:1 input MUX which is ideal for redundant clock switchover applications. This device also includes a synchronous enable pin that forces the outputs into a fixed logic state. Enable or disable state is initiated only after the outputs are in a LOW state to eliminate the possibility of a runt clock pulse. Features • 2 GHz maximum output frequency • 25 ps maximum output-to-output skew • 150 ps part-to-part skew • 350 ps typical propagation delay • 2:1 differential MUX input • 2.5 / 3.3 V operating range • LVPECL and HSTL input compatible • 16-lead TSSOP package • Temperature range –40°C to +85°C MC100ES6130 ORDERING INFORMATION Device Package MC100ES6130DT TSSOP-16 MC100ES6130DTR2 TSSOP-16 DT SUFFIX 16 LEAD TSSOP PACKAGE CASE 948F Figure 1. 16-Lead Pinout (Top View) and Logic Diagram IN1 VCC IN0 15 16 14 13 12 11 10 9 EN IN0 IN1 VEE IN_SEL Q1 Q0 Q2 Q0 2 1 3 4 5 6 8 7 Q1 Q2 Q3 Q3 D Q Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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