MOTOROLA CMOS LOGIC DATA

7

MC14534B

APPLICATIONS INFORMATION

Figure 1. Cascade Operation

* Carry Out is high for a single clock period when all five BCD stages go to zero.

(Carry Out also goes high when MR is applied.)

VDD

CLOCK

CLOCK A

CLOCK A

En

C

Q4

Cout*

1/2

MC14518B

MC14534B

MC14534B

Figure 2. Forcing a BCD Stage to the Q Outputs

When the Q outputs of a given stage are required, this configuration will

lock up the selected stage within four clock cycles. The select line feedback

may be hardwired or switched.

CLOCK

BCD FOR

SELECTED

STAGE

Q0

CLOCK A

Q1

Q2

Q3

SC

DS5

DS4

DS3

DS2

DS1

MC14534B

MODE B

CLOCK A

Eout

MR

Cext

DS2

DS1

MODE A

Q0

3–ST BCD

Cext

CLOCK B

VDD

3–ST DIG

DS4

Q3

5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

13

11

12

21

22

23

24

Cout

DS3

Q2

Q1

DS5

VSS

SC

SR

PIN ASSIGNMENT