MC145446A

MOTOROLA

9

DTMF IN

DTMF Receive Input (AGC Amp Input) (Pin 5)

This pin is the receive DTMF signal input. It is enabled

when the device is in the DTMF receive mode.

AGC OUT

AGC Output (Pin 6)

This pin is used by the manufacturer to test the auto gain

control amplifier. It should be held open in normal operation.

DSI

Driver Summing Input (Pin 22)

This pin is the inverting input of the line driver. An external

signal may be transmitted through an external series resistor

RDSI. The differential gain GDSI = (VTxA1 – VTxA2)/VDSI

is determined by the following equation:

GDSI = – 2Rf / RDSI, Rf X 20 kΩ

Note that the programmable transmit attenuator does not

affect in this case.

The DSI pin should be held open when not in use.

CDA

Carrier Detect Level/CPTD Level Control (Pin 4)

The carrier/call progress tone detect level is adjusted by

the CDA pin voltage.

When this pin is held open, the CDA voltage is set to

1.25 V (VCC = ± 5 V) by an internal divider. Then the detect

level is set at – 44 dBm (typ) for off to on, and – 47 dBm (typ)

for on to off, and the hysteresis is set minimum 2 dB. This pin

has a very high input impedance so it should be connected to

GND with a 0.1

µF capacitor to keep it under the regulations.

An external voltage may be applied to this pin to adjust the

carrier detect threshold. The following equations may be

used to find the CDA voltage required for a given threshold

voltage:

VCDA = 245 × Von

VCDA = 347 × Voff

TLA

Transmit Carrier Level Adjust (Pin 11)

This pin is used to adjust the transmit carrier level that is

determined by the value of the resistor (RTLA) connected

between this pin and the GND. The maximum level can be

obtained when this pin is shorted to GND (RTLA = 0).

FTLC1

FSK Filter Test (Pin 28)

This pin is a high–impedence filter output. It may be used

for testing the FSK filter characteristics, and is reserved for

manufacturer’s use only. In normal operation, this pin should

be decoupled to Vref with a 0.1 µF capacitor.

FTLC2

DTMF Receive Low Group Filter Test (Pin 7)

This pin is a high–impedence filter output. It may be used

for testing the DTMF receive high goup bandpass filter char-

acteristics, and is reserved for manufacturer’s use only. In

normal operation, this pin should be decoupled to Vref with a

0.1

µF capacitor.

FTLC3

DTMF Receive High Group Filter Test (Pin 8)

This pin is a high–impedence filter output. It may be used

for testing the DTMF receive high group bandpass filter char-

acteristics, and is reserved for manufacturer’s use only. In

normal operation, this pin should be decoupled to Vref with a

0.1

µF capacitor.

SERIAL CONTROL INTERFACE

The following six functions are determined by the 16 bits of

serial data in the control register.

T3

T2

T1

T0

CD1

CD0

A2

A1

A0

TRANSMIT TONE

FREQUENCY

:

CARRIER DETECT TIME

:

CHANNEL

:

SQ

TRANSMIT SQUELCH

:

FUNCTION MODE

:

TRANSMIT ATTENUATOR

:

CH

A3

CONTROL REGISTER

M2

M1

M0

M3

The received DTMF tones are indicated by the four bits of

data in the status register.

D3

D2

D1

D0

RECEIVE TONE FREQUENCY :

STATUS REGISTER

Figure 1 presents the timing diagram of 16–bit control reg-

ister input and four–bit status output. When the R/W pin is in

logic low, the 16–bit data is captured into the control register

at the rising edge of SCK and latched in the mode control

logic to update the function mode at logic high input to the E

pin. When the R/W pin is in logic high, the status register is

selected to read out the received DTMF data, the four–bit

data in the DTMF decoder is loaded into the status register,

and the first bit (D0) is presented at the Data I/O on the rising

edge of E. The following bits are repeatedly shifted out as

D1–D2–D3–D0–D1–... by the rising edges of SCK.

CONTROL REGISTER BIT MAP DESCRIPTION

FUNCTION MODE (M3 to M0)

One of the following modes is selected from the four–bit

data (M3 to M0) shown in Table 1. Table 2 presents each out-

put status; the functions are described below.