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AD5371BBCZ Datenblatt(PDF) 1 Page - Analog Devices |
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AD5371BBCZ Datenblatt(HTML) 1 Page - Analog Devices |
1 / 25 page 40-Channel, 14-Bit Serial Input, Voltage-Output DAC Preliminary Technical Data AD5371 Rev. P rF Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved. FEATURES 40-channel DAC in 80 Lead LQFP and 100 Ball CSPBGA Guaranteed monotonic to 14 bits Maximum output voltage span of 4 × VREF (20 V) Nominal output voltage range of -4 V to +8 V Multiple, Independent output spans available System calibration function allowing user-programmable offset and gain Channel grouping and addressing features Thermal Monitor Function DSP/microcontroller-compatible serial interface LVDS serial interface 2.5 V to 5.5 V JEDEC-compliant digital levels Power-on reset Digital reset (RESET) Clear function to user-defined SIGGND (CLR pin) Simultaneous update of DAC outputs (LDAC pin) APPLICATIONS Level setting in automatic test equipment (ATE) Variable optical attenuators (VOA) Optical switches Industrial control systems Instrumentation FUNCTIONAL BLOCK DIAGRAM CONTROL REGISTER STATE MACHINE 14 POWER-ON RESET SPI/LVDS SYNC SDI SCLK SYNC SDI SCLK SDO BUSY RESET CLR AD5371 SERIAL INTERFACE 14 VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 VOUT13 VOUT14 VOUT15 SIGGND1 14 14 14 DAC 0 REGISTER 14 14 8 8 14 14 14 14 TO MUX 2's MUX 1 A/B SELECT REGISTER X1A REGISTER X1B REGISTER MREGISTER CREGISTER 14 MUX 2 X2A REGISTER X2B REGISTER OFS1 REGISTER 14 14 DAC 0 OUTPUT BUFFER AND POWER DOWN CONTROL OUTPUT BUFFER AND POWER DOWN CONTROL OFFSET DAC 1 BUFFER 14 14 14 DAC 7 REGISTER 14 14 14 14 14 14 MUX 1 X1A REGISTER X1B REGISTER MREGISTER CREGISTER 14 MUX 2 X2A REGISTER X2B REGISTER DAC 7 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · GROUP 1 VREF0 SIGGND0 VREF2 SIGGND2 SIGGND4 SIGGND3 VREF2 SUPPLIES GROUPS 2 TO 4 VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT16 TO VOUT39 GROUPS 2 TO 4 SAME AS GROUP 1 LDAC DVCC VDD VSS AGND DNGD 14 14 14 DAC 0 REGISTER 14 14 8 8 14 14 14 14 TO MUX 2's MUX 1 A/B SELECT REGISTER X1A REGISTER X1B REGISTER MREGISTER CREGISTER 14 MUX 2 X2A REGISTER X2B REGISTER OFS0 REGISTER 14 14 DAC 0 OUTPUT BUFFER AND POWER DOWN CONTROL OUTPUT BUFFER AND POWER DOWN CONTROL OFFSET DAC 0 BUFFER GROUP 0 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 14 14 14 DAC 7 REGISTER 14 14 14 14 14 14 MUX 1 X1A REGISTER X1B REGISTER MREGISTER CREGISTER 14 MUX 2 X2A REGISTER X2B REGISTER DAC 7 BUFFER VREF1 5371-0001 Figure 1. AD5371—Protected by U.S. Patent No. 5,969,657; other patents pending |
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