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ISL12028IV27AZ-T Datenblatt(PDF) 9 Page - Intersil Corporation

Teilenummer ISL12028IV27AZ-T
Bauteilbeschribung  Real Time Clock/Calendar with EEPROM
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Hersteller  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL12028IV27AZ-T Datenblatt(HTML) 9 Page - Intersil Corporation

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9
FN8233.5
October 18, 2006
Description
The ISL12028 device is a Real Time Clock with clock/
calendar, two polled alarms with integrated 512x8 EEPROM,
oscillator compensation, CPU Supervisor (Power on Reset,
Low Voltage Sensing and Watchdog Timer) and battery
backup switch.
The oscillator uses an external, low-cost 32.768kHz crystal.
All compensation and trim components are integrated on the
chip. This eliminates several external discrete components
and a trim capacitor, saving board area and component cost.
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, Seconds. The Calendar has
separate registers for Date, Month, Year and Day-of-week.
The calendar is correct through 2099, with automatic leap
year correction.
The Dual Alarms can be set to any Clock/Calendar value for
a match. For instance, every minute, every Tuesday, or 5:23
AM on March 21. The alarms can be polled in the Status
Register or can provide a hardware interrupt (IRQ/FOUT
Pin). There is a repeat mode for the alarms allowing a
periodic interrupt.
The IRQ/FOUTpin may be software selected to provide a
frequency output of 1Hz, 4096Hz, or 32,768Hz or inactive.
The ISL12028 device integrates CPU Supervisory functions
(POR, WDT) and Battery Switch. There is Power-On-Reset
(RESET) output with 250ms delay from power on when the
VDD supply crosses the VRESET threshold for the device. It
will also assert RESET when VDD goes below the specified
VRESET threshold for the device. The VRESET threshold is
selectable via VTS2/VTS1/VTS0 registers to five (5) pre-
selected levels. There is WatchDog Timer (WDT) with 3
selectable time-out periods (0.25s, 0.75s and 1.75s) and
disabled setting. The WatchDog Timer activates the RESET
pin when it expires. Normally, the I2C Interface is disabled
when the RESET output is active, but this can be changed
by using a register bit to enable I2C operation in battery
backup mode.
The device offers a backup power input pin. This VBAT pin
allows the device to be backed up by battery or SuperCap.
The entire ISL12028 device is fully operational from 2.7 to
5.5V and the clock/calendar portion of the ISL12028 device
remains fully operational down to 1.8V (Standby Mode).
The ISL12028 device provides 4k bits of EEPROM with 8
modes of BlockLock™ control. The BlockLock allows a safe,
secure memory for critical user and configuration data, while
allowing a large user storage area.
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device. The input buffer on this pin is always active (not
gated). The pull-up resistor on this pin must use the same
voltage source as VDD.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It has an open drain output and may be wire
ORed with other open drain or open collector outputs. The
input buffer is always active (not gated).
This open drain output requires the use of a pull-up resistor.
The pull-up resistor on this pin must use the same voltage
source as VDD. The output circuitry controls the fall time of
the output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz I2C interface
speed.
VBAT
This input provides a backup supply voltage to the device.
VBAT supplies power to the device in the event the VDD
supply fails. This pin can be connected to a battery, a
SuperCap or tied to ground if not used.
IRQ/FOUT (Interrupt Output/Frequency Output)
This dual function pin can be used as an interrupt or
frequency output pin. The IRQ/FOUT mode is selected via
the frequency out control bits of the control/status register.
• Interrupt Mode. The pin provides an interrupt signal
output. This signal notifies a host processor that an alarm
has occurred and requests action. It is an open drain
active low output.
• Frequency Output Mode. The pin outputs a clock signal
which is related to the crystal frequency. The frequency
output is user selectable and enabled via the I2C bus. It is
an open drain output.
RESET
The RESET signal output can be used to notify a host
processor that the watchdog timer has expired or the VDD
voltage supply has dipped below the VRESET threshold. It is
an open drain, active LOW output. Recommended value for
the pull-up resistor is 10k
Ω. If unused it can be tied to
ground.
X1, X2
The X1 and X2 pins are the input and output, respectively, of
an inverting amplifier. An external 32.768kHz quartz crystal
is used with the ISL12028 to supply a timebase for the real
time clock. Internal compensation circuitry provides high
accuracy over the operating temperature range from
-40°C to +85°C. This oscillator compensation network can
be used to calibrate the crystal timing accuracy over
temperature either during manufacturing or with an external
temperature sensor and microcontroller for active
compensation. X2 is intended to drive a crystal only, and
should not drive any external circuit.
ISL12028


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