Datenblatt-Suchmaschine für elektronische Bauteile |
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MC141541P Datenblatt(PDF) 3 Page - Motorola, Inc |
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MC141541P Datenblatt(HTML) 3 Page - Motorola, Inc |
3 / 16 page MC141541 3 MOTOROLA ABSOLUTE MAXIMUM RATINGS Voltage Referenced to VSS Symbol Characteristic Value Unit VDD Supply Voltage – 0.3 to + 7.0 V Vin Input Voltage VSS – 0.3 to VDD + 0.3 V Id Current Drain per Pin Excluding VDD and VSS 25 mA Ta Operating Temperature Range 0 to 85 °C Tstg Storage Temperature Range – 65 to + 150 °C NOTE: Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteris- tics tables or Pin Description section. AC ELECTRICAL CHARACTERISTICS (VDD = VDD(A) = 5.0 V, VSS = VSS(A) = 0 V, TA = 25°C, Voltage Referenced to VSS) Symbol Characteristic Min Typ Max Unit tr tf Output Signal (R, G, B, FBKG and HTONE/PWMCK) Cload = 30 pF, see Figure 1 Rise Time Fall Time — — — — 6 6 ns ns FHFLB HFLB Input Frequency — — 110 kHz DC CHARACTERISTICS VDD = VDD(A) = 5.0 V ± 10%, VSS = VSS(A) = 0 V, TA = 25°C, Voltage Referenced to VSS Symbol Characteristic Min Typ Max Unit VOH High Level Output Voltage Iout = – 5 mA VDD – 0.8 — — V VOL Low Level Output Voltage Iout = 5 mA — — VSS + 0.4 V VIL VIH Digital Input Voltage (Not Including SDA and SCL) Logic Low Logic High — 0.7 VDD — — 0.3 VDD — V V VIL VIH Input Voltage of Pin SDA and SCL in SPI Mode Logic Low Logic High — 0.7 VDD — — 0.3 VDD — V V VIL VIH Input Voltage of Pin SDA and SCL in M_BUS Mode Logic Low Logic High — 0.7 VDD — — 0.3 VDD — V V III High–Z Leakage Current (R, G, B and FBKG) – 10 — + 10 µA III Input Current (Not Including RP, VCO, R, G, B, FBKG and HTONE/PWMCK) – 10 — + 10 µA IDD Supply Current (No Load on Any Output) — — + 15 mA 90% 10% 90% 10% tf tr Figure 1. Switching Characteristics This device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid applica- tions of any voltage higher than the maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. |
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