Datenblatt-Suchmaschine für elektronische Bauteile |
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NE321000 Datenblatt(PDF) 1 Page - California Eastern Labs |
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NE321000 Datenblatt(HTML) 1 Page - California Eastern Labs |
1 / 6 page PART NUMBER NE321000 PACKAGE OUTLINE CHIP SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN TYP MAX NF Noise Figure, VDS = 2 V, ID = 10 mA, f = 12 GHz dB 0.35 0.45 GA1 Associated Gain, VDS = 2 V, ID = 10 mA, f = 12 GHz dB 12.0 13.5 IDSS Saturated Drain Current, VDS = 2 V, VGS = 0 V mA 15 40 70 VP Pinch-off Voltage, VDS = 2 V, ID = 100 µA V -0.2 -0.7 -2.0 gM Transconductance, VDS = 2 V, ID = 10 µAmS 40 55 IGSO Gate to Source Leakage Current, VGS = -3 V µA 0.5 10 ULTRA LOW NOISE PSEUDOMORPHIC HJ FET NE321000 Note: 1. RF performance is determined by packaging and testing 10 samples per wafer. Wafer rejection criteria for standard devices is 2 rejects per 10 samples. DESCRIPTION NEC's NE321000 is a Hetero-Junction FET chip that utilizes the junction between Si-doped AlGaAs and undoped InGaAs to create high electron mobility. Its excellent low noise figure and high associated gain make it suitable for commercial, industrial and space applications. NEC's stringent quality assurance and test procedures assure the highest reliability and performance. FEATURES • SUPER LOW NOISE FIGURE: 0.35 dB Typ at f = 12 GHz • HIGH ASSOCIATED GAIN: 13.0 dB Typ at f = 12 GHz • GATE LENGTH: ≤0.2 µm • GATE WIDTH: 160 µm ELECTRICAL CHARACTERISTICS (TA = 25°C) Drain Current, ID (mA) NOISE FIGURE & ASSOCIATED GAIN vs. DRAIN CURRENT California Eastern Laboratories VDS = 2 V f = 12 GHz GA NF 2.0 15 14 13 12 11 30 20 10 0 0.5 1.0 1.5 |
Ähnliche Teilenummer - NE321000 |
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Ähnliche Beschreibung - NE321000 |
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